A project is to design a buzz of the control module. 2 by TAG mouth to beep.sof downloaded to the FPGA, the device will have a buzz sound issue

beep_v
......\beep.asm.rpt
......\beep.bdf
......\beep.cdf
......\beep.done
......\beep.dpf
......\beep.fit.eqn
......\beep.fit.rpt
......\beep.fit.smsg
......\beep.fit.summary
......\beep.flow.rpt
......\beep.map.eqn
......\beep.map.rpt
......\beep.map.summary
......\beep.pin
......\beep.pof
......\beep.qpf
......\beep.qsf
......\beep.qws
......\beep.sof
......\beep.tan.rpt
......\beep.tan.summary
......\beep_assignment_defaults.qdf
......\buzzer.bsf
......\buzzer.v
......\setup.tcl
......\setup.tcl.bak

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