actel fpga fusion kit operating procedures for external sram

外部SRAM实验\project\write_read_SRAM\write_read_SRAM.prj
............\.......\...............\viewdraw\viewdraw.ini
............\.......\...............\........\.f\project.lst
............\.......\...............\synthesis\.recordref
............\.......\...............\.........\SRAM.areasrr
............\.......\...............\.........\SRAM.edn
............\.......\...............\.........\SRAM.fse
............\.......\...............\.........\SRAM.htm
............\.......\...............\.........\SRAM.map
............\.......\...............\.........\SRAM.sap
............\.......\...............\.........\SRAM.sdf
............\.......\...............\.........\SRAM.srd
............\.......\...............\.........\SRAM.srm
............\.......\...............\.........\SRAM.srr
............\.......\...............\.........\SRAM.srs
............\.......\...............\.........\SRAM.tlg
............\.......\...............\.........\SRAM_drc.rpt
............\.......\...............\.........\SRAM_sdc.sdc
............\.......\...............\.........\SRAM_syn.prd
............\.......\...............\.........\SRAM_syn.prj
............\.......\...............\.........\stdout.log
............\.......\...............\.........\traplog.tlg
............\.......\...............\.........\syntmp\SRAM.msg
............\.......\...............\.........\......\SRAM.plg
............\.......\...............\.........\......\SRAM_flink.htm
............\.......\...............\.........\......\SRAM_srr.htm
............\.......\...............\.........\......\SRAM_toc.htm
............\.......\...............\.........\......\sap.log
............\.......\...............\.timulus\BtimErrors.log
............\.......\...............\........\SRAM.dsk
............\.......\...............\........\SRAM.hpj
............\.......\...............\........\files_to_build.txt
............\.......\...............\........\waveperl.log
............\.......\...............\.martgen\smartgen.aws
............\.......\...............\.imulation\meminit.dat
............\.......\...............\..........\modelsim.ini
............\.......\...............\..........\modelsim.ini.sav
............\.......\...............\hdl\SRAM_WR_RE.v
............\.......\...............\...\hdlsynchk.tcl
............\.......\...............\...\waveperl.log
............\.......\...............\designer\impl1\SRAM.adb
............\.......\...............\........\.....\SRAM.ide_des
............\.......\...............\........\.....\SRAM.pdb
............\.......\...............\........\.....\SRAM.pdb.depends
............\.......\...............\........\.....\SRAM.tcl
............\.......\...............\........\.....\SRAM_ba.sdf
............\.......\...............\........\.....\SRAM_ba.v
............\.......\...............\........\.....\designer.log
............\.......\...............\........\.....\designer_gen_ba.log
............\.......\...............\........\.....\designer_genhdl.log
............\.......\...............\........\.....\SRAM.dtf\verify.log
............\.......\...............\constraint\SRAM.pdc
............\Source File\SRAM_WR_RE.v
............\project\write_read_SRAM\designer\impl1\simulation
............\.......\...............\........\.....\SRAM.dtf
............\.......\...............\viewdraw\wir
............\.......\...............\........\vf
............\.......\...............\........\sym
............\.......\...............\........\sch
............\.......\...............\synthesis\syntmp
............\.......\...............\designer\impl1
............\.......\...............\viewdraw
............\.......\...............\synthesis
............\.......\...............\stimulus
............\.......\...............\smartgen
............\.......\...............\simulation
............\.......\...............\phy_synthesis
............\.......\...............\hdl
............\.......\...............\designer
............\.......\...............\coreconsole
............\.......\...............\constraint
............\.....

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