actel fpga kit dual-port RAM test

双端口RAM实验\Source File\rec.v
.............\...........\send.v
.............\...........\top.v
.............\...........\waveperl.log
.............\...........\writeram.v
.............\Project\DualPortRAM\DualPortRAM.prj
.............\.......\...........\viewdraw\viewdraw.ini
.............\.......\...........\........\.f\project.lst
.............\.......\...........\synthesis\.recordref
.............\.......\...........\.........\stdout.log
.............\.......\...........\.........\top.areasrr
.............\.......\...........\.........\top.edn
.............\.......\...........\.........\top.fse
.............\.......\...........\.........\top.htm
.............\.......\...........\.........\top.map
.............\.......\...........\.........\top.sap
.............\.......\...........\.........\top.sdf
.............\.......\...........\.........\top.srd
.............\.......\...........\.........\top.srm
.............\.......\...........\.........\top.srr
.............\.......\...........\.........\top.srs
.............\.......\...........\.........\top.tlg
.............\.......\...........\.........\top_drc.rpt
.............\.......\...........\.........\top_sdc.sdc
.............\.......\...........\.........\top_syn.prj
.............\.......\...........\.........\traplog.tlg
.............\.......\...........\.........\syntmp\sap.log
.............\.......\...........\.........\......\top.msg
.............\.......\...........\.........\......\top.plg
.............\.......\...........\.........\......\top_flink.htm
.............\.......\...........\.........\......\top_srr.htm
.............\.......\...........\.........\......\top_toc.htm
.............\.......\...........\.martgen\RAM2k8_work.ixf
.............\.......\...........\........\smartgen.aws
.............\.......\...........\........\RAM2k8\RAM2k8.cxf
.............\.......\...........\........\......\RAM2k8.gen
.............\.......\...........\........\......\RAM2k8.log
.............\.......\...........\........\......\RAM2k8.shx
.............\.......\...........\........\......\RAM2k8.v
.............\.......\...........\........\......\RAM2k8_R0C0.mem
.............\.......\...........\........\......\RAM2k8_R0C1.mem
.............\.......\...........\........\......\RAM2k8_R0C2.mem
.............\.......\...........\........\......\RAM2k8_R0C3.mem
.............\.......\...........\.imulation\RAM2k8_R0C0.mem
.............\.......\...........\..........\RAM2k8_R0C1.mem
.............\.......\...........\..........\RAM2k8_R0C2.mem
.............\.......\...........\..........\RAM2k8_R0C3.mem
.............\.......\...........\..........\meminit.dat
.............\.......\...........\..........\modelsim.ini
.............\.......\...........\..........\modelsim.ini.sav
.............\.......\...........\hdl\hdlsynchk.tcl
.............\.......\...........\...\rec.v
.............\.......\...........\...\send.v
.............\.......\...........\...\top.v
.............\.......\...........\...\writeram.v
.............\.......\...........\designer\impl1\designer.log
.............\.......\...........\........\.....\designer_genhdl.log
.............\.......\...........\........\.....\top.adb
.............\.......\...........\........\.....\top.ide_des
.............\.......\...........\........\.....\top.pdb
.............\.......\...........\........\.....\top.pdb.depends
.............\.......\...........\........\.....\top.stp
.............\.......\...........\........\.....\top.tcl
.............\.......\...........\........\.....\..._fp\$$FlashPro_FPBBALTLPT1.L$$
.............\.......\...........\........\.....\......\top.log
.............\.......\...........\........\.....\......\top.pro
.............\.......\...........\........\.....\......\projectData\top.pdb
.............\.......\...........\........\.....\....dtf\verify.log
.............\.......\...........\........\.....\..._fp\projectData
.............\.......\...........\........\.....\top_fp
.............\.......\...........\........\.....\top.dtf
.............\.......\...........\........\.....\simulation
...........

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