actel fpga adder verilog source code, development environment in the libero

adder\adder.prj
.....\designer\impl1\adder.ide_des
.....\........\.....\designer.log
.....\........\.....\full_add.adb
.....\........\.....\full_add.dat
.....\........\.....\..........tf\verify.log
.....\........\.....\full_add.ide_des
.....\........\.....\full_add.pdb
.....\........\.....\full_add.pdb.depends
.....\........\.....\full_add.stp
.....\........\.....\full_add.tcl
.....\........\.....\full_adder.ide_des
.....\........\.....\half_adder.ide_des
.....\hdl\full_add.v
.....\simulation\modelsim.ini
.....\..........\modelsim.log
.....\..........\presynth\full_add\verilog.psm
.....\..........\........\........\_primary.dat
.....\..........\........\........\_primary.dbs
.....\..........\........\........\_primary.vhd
.....\..........\........\stimulus\verilog.psm
.....\..........\........\........\_primary.dat
.....\..........\........\........\_primary.dbs
.....\..........\........\........\_primary.vhd
.....\..........\........\testbench\verilog.psm
.....\..........\........\.........\_primary.dat
.....\..........\........\.........\_primary.dbs
.....\..........\........\.........\_primary.vhd
.....\..........\........\_info
.....\..........\........\_vmake
.....\..........\run.do
.....\.martgen\smartgen.aws
.....\.timulus\BtimErrors.log
.....\........\files_to_build.txt
.....\........\full_add.dsk
.....\........\full_add.hpj
.....\........\full_add_tbench.btim
.....\........\full_add_tbench.v
.....\........\waveperl.log
.....\.ynthesis\.recordref
.....\.........\backup\full_add.srr
.....\.........\full_add.areasrr
.....\.........\full_add.edn
.....\.........\full_add.fse
.....\.........\full_add.htm
.....\.........\full_add.map
.....\.........\full_add.pdc
.....\.........\full_add.sap
.....\.........\full_add.sdf
.....\.........\full_add.so
.....\.........\full_add.srd
.....\.........\full_add.srm
.....\.........\full_add.srr
.....\.........\full_add.srs
.....\.........\full_add.szr
.....\.........\full_add.tlg
.....\.........\full_add_sdc.sdc
.....\.........\full_add_syn.prj
.....\.........\run_options.txt
.....\.........\stdout.log
.....\.........\.yntmp\full_add.plg
.....\.........\......\full_add_flink.htm
.....\.........\......\full_add_srr.htm
.....\.........\......\full_add_toc.htm
.....\.........\......\sap.log
.....\.........\traplog.tlg
.....\viewdraw\vf\project.lst
.....\........\viewdraw.ini
.....\designer\impl1\full_add.dtf
.....\........\.....\simulation
.....\simulation\presynth\full_add
.....\..........\........\stimulus
.....\..........\........\testbench
.....\..........\........\_temp
.....\designer\impl1
.....\simulation\presynth
.....\.ynthesis\backup
.....\.........\coreip
.....\.........\syntmp
.....\viewdraw\sch
.....\........\sym
.....\........\vf
.....\........\wir
.....\component
.....\constraint
.....\coreconsole
.....\designer
.....\hdl
.....\phy_synthesis
.....\simulation
.....\smartgen
.....\stimulus
.....\synthesis
.....\viewdraw
adder

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