The design of real-time clock, the clock through the SPI bus to change the initial value.

shishizhong\.lso
...........\clock.v
...........\clock2.v
...........\netgen\synthesis\TOP_module_synthesis.nlf
...........\......\.........\TOP_module_synthesis.v
...........\regester.v
...........\runnian.v
...........\shishizhong.ise
...........\shishizhong.ise_ISE_Backup
...........\shishizhong.ntrc_log
...........\SPI.v
...........\testREG.v
...........\test_clock2.v
...........\test_spi.v
...........\test_top.v
...........\test_TOPmodule.v
...........\top.v
...........\TOP_module.cmd_log
...........\TOP_module.lso
...........\TOP_module.ngc
...........\TOP_module.ngr
...........\TOP_module.prj
...........\TOP_module.stx
...........\TOP_module.syr
...........\TOP_module.v
...........\TOP_module.xst
...........\TOP_module_summary.html
...........\xst\dump.xst\TOP_module.prj\ntrc.scr
...........\...\work\hdllib.ref
...........\...\....\vlg13\runnian.bin
...........\...\....\...20\clock.bin
...........\...\....\...4C\_t_o_p__module.bin
...........\...\....\...52\clock2.bin
...........\...\....\...65\regester.bin
...........\...\....\....F\top.bin
...........\...\....\...74\_s_p_i.bin
...........\_xmsgs\netgen.xmsgs
...........\......\xst.xmsgs
...........\__ISE_repository_shishizhong.ise_.lock
...........\xst\dump.xst\TOP_module.prj\ngx\notopt
...........\...\........\..............\...\opt
...........\...\........\..............\ngx
...........\...\........\TOP_module.prj
...........\...\work\vlg13
...........\...\....\vlg20
...........\...\....\vlg4C
...........\...\....\vlg52
...........\...\....\vlg65
...........\...\....\vlg6F
...........\...\....\vlg74
...........\netgen\synthesis
...........\xst\dump.xst
...........\...\projnav.tmp
...........\...\work
...........\netgen
...........\xst
...........\_xmsgs
shishizhong

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