fpga vhdl output pwm' s program has been developed plate test, absolutely free.

15-PWM信号输出
..............\bcd_ascii.bsf
..............\cmp_state.ini
..............\counter.bsf
..............\counter.v
..............\counter.vhd
..............\db
..............\..\add_sub_2nh.tdf
..............\..\add_sub_5nh.tdf
..............\..\add_sub_bqh.tdf
..............\..\add_sub_eoh.tdf
..............\..\add_sub_foh.tdf
..............\..\add_sub_ioh.tdf
..............\..\add_sub_koh.tdf
..............\..\add_sub_ndh.tdf
..............\..\add_sub_orh.tdf
..............\..\add_sub_rrh.tdf
..............\..\prev_cmp_pwm_gen.asm.qmsg
..............\..\prev_cmp_pwm_gen.fit.qmsg
..............\..\prev_cmp_pwm_gen.map.qmsg
..............\..\prev_cmp_pwm_gen.qmsg
..............\..\prev_cmp_pwm_gen.tan.qmsg
..............\..\pwm_gen.asm.qmsg
..............\..\pwm_gen.cbx.xml
..............\..\pwm_gen.cmp.cdb
..............\..\pwm_gen.cmp.hdb
..............\..\pwm_gen.cmp.logdb
..............\..\pwm_gen.cmp.rdb
..............\..\pwm_gen.cmp.tdb
..............\..\pwm_gen.cmp0.ddb
..............\..\pwm_gen.dbp
..............\..\pwm_gen.db_info
..............\..\pwm_gen.eco.cdb
..............\..\pwm_gen.fit.qmsg
..............\..\pwm_gen.hier_info
..............\..\pwm_gen.hif
..............\..\pwm_gen.map.cdb
..............\..\pwm_gen.map.hdb
..............\..\pwm_gen.map.logdb
..............\..\pwm_gen.map.qmsg
..............\..\pwm_gen.pre_map.cdb
..............\..\pwm_gen.pre_map.hdb
..............\..\pwm_gen.psp
..............\..\pwm_gen.pss
..............\..\pwm_gen.rtlv.hdb
..............\..\pwm_gen.rtlv_sg.cdb
..............\..\pwm_gen.rtlv_sg_swap.cdb
..............\..\pwm_gen.sgdiff.cdb
..............\..\pwm_gen.sgdiff.hdb
..............\..\pwm_gen.signalprobe.cdb
..............\..\pwm_gen.sld_design_entry.sci
..............\..\pwm_gen.sld_design_entry_dsc.sci
..............\..\pwm_gen.syn_hier_info
..............\..\pwm_gen.tan.qmsg
..............\..\pwm_gen.tis_db_list.ddb
..............\..\pwm_gen_cmp.qrpt
..............\..\pwm_gen_sim.qrpt
..............\pwm.bsf
..............\pwm.v
..............\pwm.vhd
..............\pwm_counter.bsf
..............\pwm_counter.v
..............\pwm_counter.vhd
..............\pwm_gen.asm.rpt
..............\pwm_gen.bdf
..............\pwm_gen.cdf
..............\pwm_gen.done
..............\pwm_gen.fit.eqn
..............\pwm_gen.fit.rpt
..............\pwm_gen.fit.smsg
..............\pwm_gen.fit.summary
..............\pwm_gen.flow.rpt
..............\pwm_gen.map.eqn
..............\pwm_gen.map.rpt
..............\pwm_gen.map.summary
..............\pwm_gen.pin
..............\pwm_gen.pof
..............\pwm_gen.qpf
..............\pwm_gen.qsf
..............\pwm_gen.qws
..............\pwm_gen.sim.rpt
..............\pwm_gen.sof
..............\pwm_gen.tan.rpt
..............\pwm_gen.tan.summary
..............\pwm_gen.vwf
..............\pwm_gen_assignment_defaults.qdf
..............\serialport_tx.bsf
..............\serialport_tx.v
..............\serialport_tx.vhd

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