libero FPGA environment described ProASIC3/EFlash_ROM simulation routines,

FlashROM\FlashROM实验例程.pdf
........\....._ROM\designer\impl1\designer.log
........\.........\........\.....\RDROM_top\projectData\RDROM_top.stp
........\.........\........\.....\.........\RDROM_top.log
........\.........\........\.....\.........\RDROM_top.pro
........\.........\........\.....\RDROM_top.adb
........\.........\........\.....\..........dtf\verify.log
........\.........\........\.....\RDROM_top.ide_des
........\.........\........\.....\RDROM_top.lok
........\.........\........\.....\RDROM_top.stp
........\.........\........\.....\RDROM_top.tcl
........\.........\........\.....\simulation\postlayout\@r@d@r@o@m_top\verilog.psm
........\.........\........\.....\..........\..........\..............\_primary.dat
........\.........\........\.....\..........\..........\..............\_primary.vhd
........\.........\........\.....\..........\..........\stimulus\verilog.psm
........\.........\........\.....\..........\..........\........\_primary.dat
........\.........\........\.....\..........\..........\........\_primary.vhd
........\.........\........\.....\..........\..........\tb_clock_minmax\verilog.psm
........\.........\........\.....\..........\..........\...............\_primary.dat
........\.........\........\.....\..........\..........\...............\_primary.vhd
........\.........\........\.....\..........\..........\.estbench\verilog.psm
........\.........\........\.....\..........\..........\.........\_primary.dat
........\.........\........\.....\..........\..........\.........\_primary.vhd
........\.........\........\.....\..........\..........\_info
........\.........\Flash_ROM.prj
........\.........\hdl\ctrl_ROM.v
........\.........\...\RDROM_top.v
........\.........\...\send.v
........\.........\...\Sim_top.v
........\.........\simulation\flashROM.mem
........\.........\..........\meminit.dat
........\.........\..........\modelsim.ini
........\.........\..........\modelsim.ini.sav
........\.........\..........\modelsim.log
........\.........\..........\presynth\@r@d@r@o@m_top\verilog.psm
........\.........\..........\........\..............\_primary.dat
........\.........\..........\........\..............\_primary.vhd
........\.........\..........\........\.sim_top\verilog.psm
........\.........\..........\........\........\_primary.dat
........\.........\..........\........\........\_primary.vhd
........\.........\..........\........\ctrl_@r@o@m\verilog.psm
........\.........\..........\........\...........\_primary.dat
........\.........\..........\........\...........\_primary.vhd
........\.........\..........\........\flash@r@o@m\verilog.psm
........\.........\..........\........\...........\_primary.dat
........\.........\..........\........\...........\_primary.vhd
........\.........\..........\........\send\verilog.psm
........\.........\..........\........\....\_primary.dat
........\.........\..........\........\....\_primary.vhd
........\.........\..........\........\.timulus\verilog.psm
........\.........\..........\........\........\_primary.dat
........\.........\..........\........\........\_primary.vhd
........\.........\..........\........\tb_clock_minmax\verilog.psm
........\.........\..........\........\...............\_primary.dat
........\.........\..........\........\...............\_primary.vhd
........\.........\..........\........\.estbench\verilog.psm
........\.........\..........\........\.........\_primary.dat
........\.........\..........\........\.........\_primary.vhd
........\.........\..........\........\_info
........\.........\..........\run.do
........\.........\..........\vsim.wlf
........\.........\..........\wave.do
........\.........\.martgen\flashROM\flashROM.cxf
........\.........\........\........\flashROM.gen
........\.........\........\........\flashROM.log
........\.........\........\........\flashROM.mem
........\.........\........\........\flashROM.ufc
........\.........\........\........\flashROM.v
........\.........\........\flashROM_work.ixf
........\.........\........\smartgen.aws
........\.........\.timulus\BtimErrors.log
........\.........\.

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