VHDL-based FPGA and external memory write projects with source code

sdramtest\.metadata\.lock
.........\.........\.log
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.........\.........\........\....................\hello_world_0_syslib.1275635608453.pdom
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.........\.........\........\.........................\hello_world_0.sc
.........\.........\........\.........................\hello_world_0_syslib.sc
.........\.........\........\.........................\specs.c
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.........\.........\........\.....................ui\dialog_settings.xml
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