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DDS_PHASE

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 1.17mb
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Introduction - If you have any usage issues, please Google them yourself
DDS BUILDER and VHDL-based digital phase shift number written sources, 760Hz waveform measured by the DA good hands there is no high-speed DA, unable to continue testing. Reference
Packet file list
(Preview for download)
DDS_PHASE\constant.ipx
.........\constant.mdl
.........\constant.mdlxml
.........\constant.qip
.........\constant_add.tcl
.........\.........dspbuilder\constant.flow.rpt
.........\...................\constant.map.rpt
.........\...................\constant.map.summary
.........\...................\constant.qpf
.........\...................\constant.qsf
.........\...................\constant.sdc
.........\...................\db\alt_dspbuilder_clock.jvgen_cache.xml
.........\...................\..\alt_dspbuilder_clock.vhd
.........\...................\..\alt_dspbuilder_clock_GNF343OQUJ.vhd
.........\...................\..\constant.ae.hdb
.........\...................\..\constant.cbx.xml
.........\...................\..\constant.cmp.rdb
.........\...................\..\constant.db_info
.........\...................\..\constant.hier_info
.........\...................\..\constant.hif
.........\...................\..\constant.lpc.html
.........\...................\..\constant.lpc.rdb
.........\...................\..\constant.lpc.txt
.........\...................\..\constant.map.qmsg
.........\...................\..\constant.pre_map.cdb
.........\...................\..\constant.pre_map.hdb
.........\...................\..\constant.rtlv.hdb
.........\...................\..\constant.rtlv_sg.cdb
.........\...................\..\constant.rtlv_sg_swap.cdb
.........\...................\..\constant.sld_design_entry_dsc.sci
.........\...................\..\constant.smart_action.txt
.........\...................\..\constant_1.jvgen_cache.xml
.........\...................\..\constant_1.vhd
.........\...................\..\constant_1_GN.vhd
.........\...................\..\logic_util_heursitic.dat
.........\...................\incremental_db\README
.........\...................\.p\constant\constant.ipx
.........\...................\reports\constant\constant_1_example.vhd
.........\...................\.......\........\output_file.map
.........\...................\.......\........\output_file.pof
.........\DDS_phase.ipx
.........\DDS_phase.mdl
.........\DDS_phase.mdlxml
.........\DDS_phase.qip
.........\DDS_phase_add.tcl
.........\..........dspbuilder\8to32.vhd
.........\....................\8to32.vhd.bak
.........\....................\clockdiv.bsf
.........\....................\clockdiv.v
.........\....................\clockdiv.v.bak
.........\....................\clockdiv.vwf
.........\....................\constant_1_example.bsf
.........\....................\db\add_sub_8ph.tdf
.........\....................\..\add_sub_kak.tdf
.........\....................\..\altsyncram_ucq3.tdf
.........\....................\..\alt_dspbuilder_AROUND.vhd
.........\....................\..\alt_dspbuilder_ASAT.vhd
.........\....................\..\alt_dspbuilder_cast.jvgen_cache.xml
.........\....................\..\alt_dspbuilder_cast.vhd
.........\....................\..\alt_dspbuilder_cast_GN3TEBP4UY.vhd
.........\....................\..\alt_dspbuilder_cast_GN5D52DF5S.vhd
.........\....................\..\alt_dspbuilder_cast_GNJFUTI4QZ.vhd
.........\....................\..\alt_dspbuilder_clock.jvgen_cache.xml
.........\....................\..\alt_dspbuilder_clock.vhd
.........\....................\..\alt_dspbuilder_clock_GNF343OQUJ.vhd
.........\....................\..\alt_dspbuilder_delay.jvgen_cache.xml
.........\....................\..\alt_dspbuilder_delay.vhd
.........\....................\..\alt_dspbuilder_delay_GNIBYDG2XV.vhd
.........\....................\..\alt_dspbuilder_gnd.jvgen_cache.xml
.........\....................\..\alt_dspbuilder_gnd.vhd
.........\....................\..\alt_dspbuilder_gnd_GN.vhd
.........\....................\..\alt_dspbuilder_lut.jvgen_cache.xml
.........\....................\..\alt_dspbuilder_lut.vhd
.........\....................\..\alt_dspbuilder_lut_GNONYODDEP.hex
.........\....................\..\alt_dspbuilder_lut_GNONYODDEP.vhd
.........\....................\..\alt_dspbuilder_parallel_adder.jvgen_cache.xml
.........\....................\..\alt_dspbuilder_parallel_adder.vhd
.........\....................\..\alt_d
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