Synchronous fifo, there are test vectors, by using modelsim simulation.

fifo_syn\fifo_syn_flag.v
........\fifo_syn_flag.v.bak
........\fifo_syn_ram.v
........\fifo_syn_rdaddr_gen.v
........\fifo_syn_top.v
........\fifo_syn_top.v.bak
........\fifo_syn_wraddr_gen.v
........\fifo_top_tb.v
........\fifo_top_tb.v.bak
........\modelsim.ini
........\reference\syn_fifo2.v
........\.........\同步FIFO设计.doc
........\syn_fifo2.v.bak
........\transcript
........\vsim.wlf
........\work\fifo_syn_flag\verilog.asm
........\....\.............\_primary.dat
........\....\.............\_primary.vhd
........\....\.........ram\verilog.asm
........\....\............\_primary.dat
........\....\............\_primary.vhd
........\....\..........daddr_gen\verilog.asm
........\....\...................\_primary.dat
........\....\...................\_primary.vhd
........\....\.........top\verilog.asm
........\....\............\_primary.dat
........\....\............\_primary.vhd
........\....\.........wraddr_gen\verilog.asm
........\....\...................\_primary.dat
........\....\...................\_primary.vhd
........\....\.....top_tb\verilog.asm
........\....\...........\_primary.dat
........\....\...........\_primary.vhd
........\....\syn_fifo2\verilog.asm
........\....\.........\_primary.dat
........\....\.........\_primary.vhd
........\....\_info
........\使用说明请参看右侧注释====〉〉.txt
........\work\fifo_syn_flag
........\....\fifo_syn_ram
........\....\fifo_syn_rdaddr_gen
........\....\fifo_syn_top
........\....\fifo_syn_wraddr_gen
........\....\fifo_top_tb
........\....\syn_fifo2
........\reference
........\work
fifo_syn

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