Verilog realization of CISC, and a courseware, former school teacher, when an example of good

cisc\address_reg\address_reg.asm.rpt
....\...........\address_reg.done
....\...........\address_reg.fit.eqn
....\...........\address_reg.fit.rpt
....\...........\address_reg.fit.summary
....\...........\address_reg.flow.rpt
....\...........\address_reg.map.eqn
....\...........\address_reg.map.rpt
....\...........\address_reg.map.summary
....\...........\address_reg.pin
....\...........\address_reg.qpf
....\...........\address_reg.qsf
....\...........\address_reg.qws
....\...........\address_reg.tan.rpt
....\...........\address_reg.tan.summary
....\...........\address_reg.v
....\...........\cmp_state.ini
....\...........\db\address_reg.asm.qmsg
....\...........\..\address_reg.cbx.xml
....\...........\..\address_reg.cmp.cdb
....\...........\..\address_reg.cmp.hdb
....\...........\..\address_reg.cmp.rdb
....\...........\..\address_reg.cmp.tdb
....\...........\..\address_reg.cmp0.ddb
....\...........\..\address_reg.db_info
....\...........\..\address_reg.eco.cdb
....\...........\..\address_reg.fit.qmsg
....\...........\..\address_reg.hier_info
....\...........\..\address_reg.hif
....\...........\..\address_reg.map.cdb
....\...........\..\address_reg.map.hdb
....\...........\..\address_reg.map.qmsg
....\...........\..\address_reg.pre_map.cdb
....\...........\..\address_reg.pre_map.hdb
....\...........\..\address_reg.psp
....\...........\..\address_reg.rtlv.hdb
....\...........\..\address_reg.rtlv_sg.cdb
....\...........\..\address_reg.rtlv_sg_swap.cdb
....\...........\..\address_reg.sgdiff.cdb
....\...........\..\address_reg.sgdiff.hdb
....\...........\..\address_reg.signalprobe.cdb
....\...........\..\address_reg.sld_design_entry.sci
....\...........\..\address_reg.sld_design_entry_dsc.sci
....\...........\..\address_reg.syn_hier_info
....\...........\..\address_reg.tan.qmsg
....\...........\..\address_reg_cmp.qrpt
....\.lu\alu.asm.rpt
....\...\alu.done
....\...\alu.fit.eqn
....\...\alu.fit.rpt
....\...\alu.fit.summary
....\...\alu.flow.rpt
....\...\alu.map.eqn
....\...\alu.map.rpt
....\...\alu.map.summary
....\...\alu.pin
....\...\alu.qpf
....\...\alu.qsf
....\...\alu.qws
....\...\alu.tan.rpt
....\...\alu.tan.summary
....\...\alu.v
....\...\cmp_state.ini
....\...\db\alu.asm.qmsg
....\...\..\alu.cbx.xml
....\...\..\alu.cmp.cdb
....\...\..\alu.cmp.hdb
....\...\..\alu.cmp.rdb
....\...\..\alu.cmp.tdb
....\...\..\alu.cmp0.ddb
....\...\..\alu.db_info
....\...\..\alu.eco.cdb
....\...\..\alu.fit.qmsg
....\...\..\alu.hier_info
....\...\..\alu.hif
....\...\..\alu.map.cdb
....\...\..\alu.map.hdb
....\...\..\alu.map.qmsg
....\...\..\alu.pre_map.cdb
....\...\..\alu.pre_map.hdb
....\...\..\alu.psp
....\...\..\alu.rtlv.hdb
....\...\..\alu.rtlv_sg.cdb
....\...\..\alu.rtlv_sg_swap.cdb
....\...\..\alu.sgdiff.cdb
....\...\..\alu.sgdiff.hdb
....\...\..\alu.signalprobe.cdb
....\...\..\alu.sld_design_entry.sci
....\...\..\alu.sld_design_entry_dsc.sci
....\...\..\alu.syn_hier_info
....\...\..\alu.tan.qmsg
....\...\..\alu_cmp.qrpt
....\instruction_reg\cmp_state.ini
....\...............\db\instruction_reg.asm.qmsg
....\...............\..\instruction_reg.cbx.xml
....\...............\..\instruction_reg.cmp.cdb
....\...............\..\instruction_reg.cmp.hdb
....\...............\..\instruction_reg.cmp.rdb
....\...............\..\instruction_reg.cmp.tdb
....\...............\..\instruction_reg.cmp0.ddb

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