handbook for verilog hdl language

试验指导手册\lab1——运行一个Verilog的设计实例.doc
............\lab2——使用正确的数据类型 .doc
............\lab3——用层次化的设计方法构建一个8bit寄存器.doc
............\lab4——行为级建模.doc
............\lab5——FSM的设计.doc
............\lab6——系统仿真与调试.doc
............\lab7——模块延时（选作）.doc
............\lab8——编译控制（选作）.doc
............\..._data\datatypes\dff_r.v
............\........\.........\jand.v
............\........\.........\jbuf.v
............\........\.........\jnor.v
............\........\.........\misch.v
............\........\.........\mux2.v
............\........\.........\top.v
............\........\.........\top.vc
............\........\mux\mux.v
............\........\...\mux_test.v
............\unix_guide.pdf
............\vi_use.pdf
............\大作业说明.txt
............\第2次上机试验要求.txt
............\第一次上机试验要求.txt
............\lab_data\datatypes
............\........\mux
............\lab_data
试验指导手册

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