Quartus CPU design based on the core components, control memory architecture

cu\cmp_state.ini
..\cu.asm.rpt
..\cu.bdf
..\cu.bsf
..\cu.done
..\cu.fit.eqn
..\cu.fit.rpt
..\cu.fit.summary
..\cu.flow.rpt
..\cu.map.eqn
..\cu.map.rpt
..\cu.map.summary
..\cu.mif
..\cu.pin
..\cu.pof
..\cu.qpf
..\cu.qsf
..\cu.qws
..\cu.sim.rpt
..\cu.sof
..\cu.tan.rpt
..\cu.tan.summary
..\cu.vwf
..\db\altsyncram_1do.tdf
..\..\altsyncram_fdo.tdf
..\..\cu.asm.qmsg
..\..\cu.cbx.xml
..\..\cu.cmp.cdb
..\..\cu.cmp.hdb
..\..\cu.cmp.logdb
..\..\cu.cmp.rdb
..\..\cu.cmp.tdb
..\..\cu.cmp0.ddb
..\..\cu.db_info
..\..\cu.eco.cdb
..\..\cu.eds_overflow
..\..\cu.fit.qmsg
..\..\cu.fnsim.cdb
..\..\cu.fnsim.hdb
..\..\cu.hier_info
..\..\cu.hif
..\..\cu.map.cdb
..\..\cu.map.hdb
..\..\cu.map.logdb
..\..\cu.map.qmsg
..\..\cu.pre_map.cdb
..\..\cu.pre_map.hdb
..\..\cu.psp
..\..\cu.rtlv.hdb
..\..\cu.rtlv_sg.cdb
..\..\cu.rtlv_sg_swap.cdb
..\..\cu.sgdiff.cdb
..\..\cu.sgdiff.hdb
..\..\cu.signalprobe.cdb
..\..\cu.sim.hdb
..\..\cu.sim.qmsg
..\..\cu.sim.rdb
..\..\cu.sim.vwf
..\..\cu.sld_design_entry.sci
..\..\cu.sld_design_entry_dsc.sci
..\..\cu.syn_hier_info
..\..\cu.tan.qmsg
..\..\cu_cmp.qrpt
..\..\cu_sim.qrpt
..\..\mux_6dc.tdf
..\ir.bdf
..\ir.bsf
..\serv_req_info.txt
..\uir.bdf
..\uir.bsf
..\upc.bdf
..\upc.bsf
..\db
cu

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