To the use of Active-VHDL simulation test 74LS138 decoder, 74LS138 decoder is a 3-wire-8 line decoder.

Design_74LS138\Design_74LS138.adf
..............\design_74ls138.lib
..............\design_74ls138.mgf
..............\Generic\contents.lib~
..............\.......\Design_74LS138.erf
..............\.......\Design_74LS138.wsp
..............\.......\Generic.cfg
..............\.......\sources.sth
..............\.......\wave.dat
..............\log\compile.log
..............\...\console.log
..............\...\find.log
..............\...\simulation.log
..............\src\Design_74LS138.bak
..............\...\Design_74LS138.VHD
..............\...\Waveform5.awf
..............\Generic
..............\log
..............\src
Design_74LS138

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