This used to measure the frequency of the FPGA, the two signals through different or later into a square wave, and then measured the number of high-pulse width and the cycle number, calculate the duty cycle of the phase, and finally the data transmitted single-chip display.

phase_FPGA\phase_FPGA.qpf
..........\phase_FPGA.qsf
..........\db\phase_FPGA.db_info
..........\..\phase_FPGA.cbx.xml
..........\..\phase_FPGA.map_bb.hdbx
..........\..\prev_cmp_phase_FPGA.qmsg
..........\..\phase_FPGA.hif
..........\..\phase_FPGA.hier_info
..........\..\phase_FPGA.psp
..........\..\phase_FPGA.syn_hier_info
..........\..\phase_FPGA.root_partition.map.atm
..........\..\phase_FPGA.root_partition.map.hdbx
..........\..\phase_FPGA.map.ecobp
..........\..\phase_FPGA.root_partition.cmp.rcf
..........\..\phase_FPGA.root_partition.cmp.hdbx
..........\..\phase_FPGA.root_partition.cmp.atm
..........\..\phase_FPGA.rpp.qmsg
..........\..\phase_FPGA.sgate.rvd
..........\..\phase_FPGA.sgate_sm.rvd
..........\..\phase_FPGA.tmw_info
..........\..\prev_cmp_phase_FPGA.map.qmsg
..........\..\prev_cmp_phase_FPGA.fit.qmsg
..........\..\prev_cmp_phase_FPGA.asm.qmsg
..........\..\prev_cmp_phase_FPGA.tan.qmsg
..........\..\phase_FPGA.sld_design_entry.sci
..........\..\phase_FPGA.eco.cdb
..........\..\phase_FPGA.map.qmsg
..........\..\phase_FPGA.rtlv_sg.cdb
..........\..\phase_FPGA.rtlv.hdb
..........\..\phase_FPGA.rtlv_sg_swap.cdb
..........\..\phase_FPGA.pre_map.hdb
..........\..\phase_FPGA.pre_map.cdb
..........\..\phase_FPGA.root_partition.map.info
..........\..\phase_FPGA.map_bb.logdb
..........\..\phase_FPGA.sgdiff.cdb
..........\..\phase_FPGA.sgdiff.hdb
..........\..\phase_FPGA.sld_design_entry_dsc.sci
..........\..\phase_FPGA.map_bb.cdb
..........\..\phase_FPGA.map_bb.hdb
..........\..\phase_FPGA.map.cdb
..........\..\phase_FPGA.map.hdb
..........\..\phase_FPGA.map.logdb
..........\..\phase_FPGA.map.bpm
..........\..\phase_FPGA.fit.qmsg
..........\..\phase_FPGA.cmp.logdb
..........\..\phase_FPGA.cmp.bpm
..........\..\phase_FPGA.cmp.ecobp
..........\..\phase_FPGA.root_partition.cmp.logdb
..........\..\phase_FPGA.root_partition.cmp.dfp
..........\..\phase_FPGA.tis_db_list.ddb
..........\..\phase_FPGA.asm.qmsg
..........\..\phase_FPGA.tan.qmsg
..........\..\phase_FPGA.cmp.tdb
..........\..\phase_FPGA.cmp0.ddb
..........\..\phase_FPGA.cmp.cdb
..........\..\phase_FPGA.signalprobe.cdb
..........\..\phase_FPGA.cmp.hdb
..........\..\phase_FPGA.cmp.rdb
..........\Fre_test.vhd
..........\epd.vhd
..........\phase_FPGA.map.summary
..........\phase_FPGA.vhd.bak
..........\phase_FPGA.vhd
..........\phase_FPGA.pin
..........\phase_FPGA.fit.smsg
..........\phase_FPGA.fit.summary
..........\phase_FPGA.sof
..........\phase_FPGA.pof
..........\phase_FPGA.tan.summary
..........\phase_FPGA.done
..........\phase_FPGA.map.rpt
..........\phase_FPGA.fit.rpt
..........\phase_FPGA.asm.rpt
..........\phase_FPGA.tan.rpt
..........\phase_FPGA.flow.rpt
..........\db
phase_FPGA

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