Quartus platform based on the use of SDRAM chip design data to enable high-speed FIFO read write speed

FIFO\buffer.v
....\buffer_r.v
....\data_generate.v
....\dual_1024RAM.v
....\dual_1024RAM_bb.v
....\dual_port_1024RAM.v
....\dual_port_1024RAM_bb.v
....\dual_port_512RAM.v
....\dual_port_512RAM_bb.v
....\FIFO.qpf
....\FIFO.v
....\FIFO_R.v
....\FIFO_W.v
....\pll_125Mhz.v
....\PLL_125Mhz_bb.v
....\SDRAM2.v
FIFO

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