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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 315kb
  • Downloaded :0次
  • Author :飘***
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
This design uses programmable logic device accompanied by a small speaker designed a music generator.
Packet file list
(Preview for download)
shiyan8
.......\db
.......\..\add_sub_olh.tdf
.......\..\prev_cmp_SONG.asm.qmsg
.......\..\prev_cmp_SONG.fit.qmsg
.......\..\prev_cmp_SONG.map.qmsg
.......\..\prev_cmp_SONG.qmsg
.......\..\prev_cmp_SONG.sim.qmsg
.......\..\prev_cmp_SONG.tan.qmsg
.......\..\SONG.asm.qmsg
.......\..\SONG.cbx.xml
.......\..\SONG.cmp.cdb
.......\..\SONG.cmp.hdb
.......\..\SONG.cmp.logdb
.......\..\SONG.cmp.rdb
.......\..\SONG.cmp.tdb
.......\..\SONG.cmp0.ddb
.......\..\SONG.db_info
.......\..\SONG.eco.cdb
.......\..\SONG.eds_overflow
.......\..\SONG.fit.qmsg
.......\..\SONG.hier_info
.......\..\SONG.hif
.......\..\SONG.map.cdb
.......\..\SONG.map.hdb
.......\..\SONG.map.logdb
.......\..\SONG.map.qmsg
.......\..\SONG.pre_map.cdb
.......\..\SONG.pre_map.hdb
.......\..\SONG.rtlv.hdb
.......\..\SONG.rtlv_sg.cdb
.......\..\SONG.rtlv_sg_swap.cdb
.......\..\SONG.sgdiff.cdb
.......\..\SONG.sgdiff.hdb
.......\..\SONG.sim.cvwf
.......\..\SONG.sim.hdb
.......\..\SONG.sim.qmsg
.......\..\SONG.sim.rdb
.......\..\SONG.sld_design_entry.sci
.......\..\SONG.sld_design_entry_dsc.sci
.......\..\SONG.syn_hier_info
.......\..\SONG.tan.qmsg
.......\..\SONG.tis_db_list.ddb
.......\..\SONG.tmw_info
.......\..\wed.wsf
.......\SONG.asm.rpt
.......\song.bsf
.......\SONG.done
.......\SONG.dpf
.......\SONG.fit.rpt
.......\SONG.fit.smsg
.......\SONG.fit.summary
.......\SONG.flow.rpt
.......\SONG.hexout
.......\SONG.map.rpt
.......\SONG.map.summary
.......\SONG.pin
.......\SONG.pof
.......\SONG.qpf
.......\SONG.qsf
.......\SONG.qws
.......\SONG.sim.rpt
.......\SONG.sof
.......\SONG.tan.rpt
.......\SONG.tan.summary
.......\SONG.vhd
.......\SONG.vwf
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