Introduction - If you have any usage issues, please Google them yourself
Designed with an asynchronous reset, enable and synchronous count-based pre-decimal counter. With five input (CLK, RST, EN, LOAD, DATA). Input clock signal CLK RST play the role of an asynchronous reset, RST = 0, reset EN clock is enabled, EN = 1, to allow loading or count LOAD is the data load control, LOAD = 0, load data to the internal register DATA is a 4-bit parallel loading of data. There are two output ports (DOUT and COUT). DOUT bit width is 4, the output count value from 0 to 9 COUT is the output carry flag, bit width is 1, when DOUT is a high level pulse output 9