FPGA serial communication port RS232-485 build, RS232 and 485 to selectively control, source-based QuartusII6.0 written in Verilog language.

db\add_sub_3rh.tdf
..\add_sub_4rh.tdf
..\add_sub_5rh.tdf
..\add_sub_8rh.tdf
..\altsyncram_fji2.tdf
..\altsyncram_hji2.tdf
..\cmpr_5mh.tdf
..\cntr_3jf.tdf
..\cntr_4ag.tdf
..\cntr_7he.tdf
..\cntr_8he.tdf
..\cntr_f7f.tdf
..\cntr_pdh.tdf
..\decode_ogi.tdf
..\mux_8ec.tdf
..\mux_jcc.tdf
..\mux_qfc.tdf
..\rs.db_info
..\rs.eco.cdb
..\rs.sim.vwf
..\rs.sld_design_entry.sci
..\wed.wsf
..\wed.zsf
div_clk.bsf
div_clk.v
rs.bdf
rs.bsf
rs.cdf
rs.qpf
rs.vwf
rs.asm.rpt
rs.done
rs.dpf
rs.fit.rpt
rs.fit.smsg
rs.fit.summary
rs.flow.rpt
rs.map.rpt
rs.map.smsg
rs.map.summary
rs.pin
rs.pof
rs.qsf
rs.qws
rs.sim.rpt
rs.sof
rs.tan.rpt
rs.tan.summary
rs_assignment_defaults.qdf
rxd.bsf
rxd.v
stp1.stp
txd.bsf
txd.v
Waveform1.vwf
db

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