Electronic Design Competition 2006, second prize, multi-function signal generator within the core of the device schematic FPGA, VHDL code with the description of the main modules, including the PLL, phase accumulator, sine lookup table algorithm and the waveform can be realized 0.005Hz ~ 20MHz multi-waveform signal generator, the frequency step value of 0.005, then the output rate of 100MSPS DAC- AD9762

SG_FPGA\add.bsf
.......\add.inc
.......\add.vhd
.......\ADD1.bsf
.......\ADD1.inc
.......\ADD1.vhd
.......\cmp.bsf
.......\cmp.inc
.......\cmp.vhd
.......\db\accum_v0e.tdf
.......\..\add_sub_6fg.tdf
.......\..\cmpr_09i.tdf
.......\..\cmpr_99i.tdf
.......\..\cntr_peh.tdf
.......\..\decode_q0f.tdf
.......\..\mux_2td.tdf
.......\..\mux_5td.tdf
.......\..\mux_dee.tdf
.......\..\signal.db_info
.......\..\signal.eco.cdb
.......\..\signal.sld_design_entry.sci
.......\decode16.bsf
.......\decode16.inc
.......\decode16.vhd
.......\mux3.bsf
.......\mux3.inc
.......\mux3.vhd
.......\or.bsf
.......\or.inc
.......\or.vhd
.......\PLL1.bsf
.......\PLL1.inc
.......\PLL1.ppf
.......\PLL1.vhd
.......\PLL1_wave0.jpg
.......\PLL1_waveforms.html
.......\signal.asm.rpt
.......\signal.bdf
.......\signal.cdf
.......\signal.done
.......\signal.dpf
.......\signal.fit.rpt
.......\signal.fit.smsg
.......\signal.fit.summary
.......\signal.flow.rpt
.......\signal.map.rpt
.......\signal.map.summary
.......\signal.pin
.......\signal.pof
.......\signal.qpf
.......\signal.qsf
.......\signal.qws
.......\signal.sof
.......\signal.tan.rpt
.......\signal.tan.summary
.......\signal_assignment_defaults.qdf
.......\X.rar
.......\db
SG_FPGA

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