Continued chapter06, from entry to the project are given some examples of applications that can help beginners learn instance by hardware description language to understand and master the basics.

Chapter-7\i2c_controller\i2c_controller.cr.mti
.........\..............\i2c_controller.mpf
.........\..............\i2c_master_bit_ctrl.v
.........\..............\i2c_master_byte_ctrl.v
.........\..............\i2c_master_defines.v
.........\..............\i2c_master_top.v
.........\..............\i2c_slave_model.v
.........\..............\timescale.v
.........\..............\transcript
.........\..............\tst_bench_top.v
.........\..............\vsim.wlf
.........\..............\wb_master_model.v
.........\..............\chart\Thumbs.db
.........\..............\.....\嗾7-11.bmp
.........\..............\.....\嗾7-12.bmp
.........\..............\.....\嗾7-14.bmp
.........\..............\.....\嗾7-15.bmp
.........\..............\.....\嗾7-16.bmp
.........\..............\.....\嗾7-17.bmp
.........\..............\.....\嗾7-18.bmp
.........\..............\.....\嗾7-21.bmp
.........\..............\.....\嗾7-22.bmp
.........\..............\.....\嗾7-23.bmp
.........\..............\chart
.........\..............\wave\Thumbs.db
.........\..............\....\i2c_master_bit_ctrl.bmp
.........\..............\....\i2c_master_byte_ctrl.bmp
.........\..............\....\i2c_master_top.bmp
.........\..............\....\i2c_slave_model.bmp
.........\..............\....\tst_bench_top.bmp
.........\..............\....\wb_master_model.bmp
.........\..............\wave
.........\..............\.ork\_info
.........\..............\....\delay\_primary.dat
.........\..............\....\.....\_primary.vhd
.........\..............\....\.....\verilog.asm
.........\..............\....\delay
.........\..............\....\i2c_master_bit_ctrl\_primary.dat
.........\..............\....\...................\_primary.vhd
.........\..............\....\...................\verilog.asm
.........\..............\....\i2c_master_bit_ctrl
.........\..............\....\............yte_ctrl\_primary.dat
.........\..............\....\....................\_primary.vhd
.........\..............\....\....................\verilog.asm
.........\..............\....\i2c_master_byte_ctrl
.........\..............\....\...........top\_primary.dat
.........\..............\....\..............\_primary.vhd
.........\..............\....\..............\verilog.asm
.........\..............\....\i2c_master_top
.........\..............\....\....slave_model\_primary.dat
.........\..............\....\...............\_primary.vhd
.........\..............\....\...............\verilog.asm
.........\..............\....\i2c_slave_model
.........\..............\....\tst_bench_top\_primary.dat
.........\..............\....\.............\_primary.vhd
.........\..............\....\.............\verilog.asm
.........\..............\....\tst_bench_top
.........\..............\....\wb_master_model\_primary.dat
.........\..............\....\...............\_primary.vhd
.........\..............\....\...............\verilog.asm
.........\..............\....\wb_master_model
.........\..............\work
.........\i2c_controller
Chapter-7

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