Written by Verilog FPGA uart interface, including transmit and receive

FPGA_UART\_13_uart_tx_test\src\ASCII码表.png
.........\................\...\fpga4fun UART.pdf
.........\................\...\pins' list.txt
.........\................\...\UART SCH.png
.........\................\...\uart_tx.v
.........\................\...\uart_tx_test.v
.........\................\uart_tx_test.done
.........\................\uart_tx_test.dpf
.........\................\uart_tx_test.fit.smsg
.........\................\uart_tx_test.fit.summary
.........\................\uart_tx_test.map.summary
.........\................\uart_tx_test.pin
.........\................\uart_tx_test.pof
.........\................\uart_tx_test.qpf
.........\................\uart_tx_test.qsf
.........\................\uart_tx_test.qws
.........\................\uart_tx_test.sof
.........\................\uart_tx_test.tan.summary
.........\................\uart_tx_test_assignment_defaults.qdf
.........\..4_uart_rx_test\src\ASCII码表.png
.........\................\...\fpga4fun UART.pdf
.........\................\...\LCD1602 SCH.png
.........\................\...\LCD1602 状态机.jpg
.........\................\...\lcd1602_drive.v
.........\................\...\pins' list.txt
.........\................\...\row1_val和row2_val中字符地址.png
.........\................\...\UART SCH.png
.........\................\...\uart_rx.v
.........\................\...\uart_rx_test.v
.........\................\uart_rx_test.done
.........\................\uart_rx_test.dpf
.........\................\uart_rx_test.fit.smsg
.........\................\uart_rx_test.fit.summary
.........\................\uart_rx_test.map.smsg
.........\................\uart_rx_test.map.summary
.........\................\uart_rx_test.pin
.........\................\uart_rx_test.pof
.........\................\uart_rx_test.qpf
.........\................\uart_rx_test.qsf
.........\................\uart_rx_test.qws
.........\................\uart_rx_test.sof
.........\................\uart_rx_test.tan.summary
.........\................\uart_rx_test_assignment_defaults.qdf
.........\..3_uart_tx_test\src
.........\..4_uart_rx_test\src
.........\_13_uart_tx_test
.........\_14_uart_rx_test
FPGA_UART

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