Verilog implementation with a 32-bit RISC processor to achieve a simple shift, addition and other basic operations.

cpu\alu\add.v
...\...\add_sixteen.v
...\...\ALU.v
...\...\four_adder.v
...\...\four_addersh.v
...\...\fulladder_gate.v
...\...\funnel_shifter.v
...\...\logic.v
...\...\multi_choice16.v
...\...\multi_choice2.v
...\...\multi_choice4.v
...\...\multi_choice8.v
...\...\shift.v
...\controller\controller.v
...\cpu.v
...\cpu.vwf
...\DataPath\decoder.v
...\........\IR.v
...\........\memory.v
...\........\mux32_32.v
...\........\ram.v
...\........\reg.v
...\........\registerfile.v
...\memory.mif
...\memory1.mif
...\readme.txt
...\alu
...\controller
...\DataPath
cpu

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