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cnt10.vhd

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 1kb
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  • Author :cheng******
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Introduction - If you have any usage issues, please Google them yourself
Design of a 10-N synchronous counter, with a clear end, a carry output. (If you change the hex, it should be as Any amendment to the procedure) Divided into synchronous and asynchronous counter counter counter two, is a typical sequential circuit, analysis of the counter can better understand Timing characteristics of the circuit. The so-called synchronous counter, that is, under the control of the clock pulse, the counter triggers the same time constitute a change The kind of counter. Asynchronous counter, also known as traveling wave counter, it s next on the counter output as a counter clock signal No, this one a tandem together to form an asynchronous counter. Asynchronous counter and synchronous counter difference is that the clock Pulse mode of delivery, but because of the asynchronous counter using wave count, so count delayed increase in the required areas of the small delay Has been greatly restricted. However, because of its simple circuit, there are still widel
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cnt10.vhd.txt
cnt10.rar
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