verilog-eg For beginners

verilog-eg

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Category : VHDL-FPGA-Verilog
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Update : 2012-11-26
Size : 27kb
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Author ：a*****
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Filename	Size	Update
第15章常用加法器设计\carry_chain_adder.v
.....................\carry_skip_adder.v
.....................\ripple_carry_adder.v
...6章常用乘法器设计\basic_base2_mul.v
.....................\basic_base2_mul_seq.v
.....................\carry_save_mult.v
.....................\ripple_carry_mult.v
...7章伽罗华域GF（q）乘法器设计\ff_const_mul.v
................................\ff_mul.v
...8章除法器设计\rest_div_int.v
.................\seq_div.v
...9章积分梳状滤波器(CIC)设计\cic3_decimator.v
..20章 CORDIC数字计算机的设计\cordic.v
...1章伪随机序列应用设计\randomization.v
...2章异步FIFO设计\async_cmp.v
...................\async_fifo.v
...................\dp_ram.v
...................\rptr_empty.v
...................\wptr_full.v
...3章 RS(204	188)译码器的设计\BM_KES.v
..............................\CheinSearch.v
..............................\ROM_INV.mif
..............................\RS(204	188)译码器说明.txt
..............................\SyndromeCalc.v
..............................\ff_mul.v
..............................\forney.v
..............................\rom_inv.v
..............................\rom_power.mif
..............................\rom_power.v
..............................\rs_decoder.v
第15章常用加法器设计
第16章常用乘法器设计
第17章伽罗华域GF（q）乘法器设计
第18章除法器设计
第19章积分梳状滤波器(CIC)设计
第20章 CORDIC数字计算机的设计
第21章伪随机序列应用设计
第22章异步FIFO设计
第23章 RS(204	188)译码器的设计

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