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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 231kb
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  • Author :鲁***
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Quartus development with a DDS-based sine wave signal generator.
Packet file list
(Preview for download)
sin_gnt\data_rom.cmp
.......\data_rom.vhd
.......\data_rom.vwf
.......\.b\singt.asm.qmsg
.......\..\singt.cbx.xml
.......\..\singt.cmp.cdb
.......\..\singt.cmp.hdb
.......\..\singt.cmp.kpt
.......\..\singt.cmp.logdb
.......\..\singt.cmp.rdb
.......\..\singt.cmp.tdb
.......\..\singt.cmp0.ddb
.......\..\singt.dbp
.......\..\singt.db_info
.......\..\singt.eco.cdb
.......\..\singt.eds_overflow
.......\..\singt.fit.qmsg
.......\..\singt.hier_info
.......\..\singt.hif
.......\..\singt.map.cdb
.......\..\singt.map.hdb
.......\..\singt.map.logdb
.......\..\singt.map.qmsg
.......\..\singt.pre_map.cdb
.......\..\singt.pre_map.hdb
.......\..\singt.psp
.......\..\singt.rtlv.hdb
.......\..\singt.rtlv_sg.cdb
.......\..\singt.rtlv_sg_swap.cdb
.......\..\singt.sgdiff.cdb
.......\..\singt.sgdiff.hdb
.......\..\singt.signalprobe.cdb
.......\..\singt.sim.hdb
.......\..\singt.sim.qmsg
.......\..\singt.sim.rdb
.......\..\singt.sim.vwf
.......\..\singt.sld_design_entry.sci
.......\..\singt.sld_design_entry_dsc.sci
.......\..\singt.syn_hier_info
.......\..\singt.tan.qmsg
.......\..\wed.zsf
.......\PLLU.bsf
.......\PLLU.cmp
.......\PLLU.ppf
.......\PLLU.vhd
.......\pllu.vwf
.......\PLLU_wave0.jpg
.......\PLLU_waveforms.html
.......\singt.asm.rpt
.......\singt.done
.......\singt.fit.rpt
.......\singt.fit.smsg
.......\singt.fit.summary
.......\singt.flow.rpt
.......\singt.map.rpt
.......\singt.map.summary
.......\singt.pin
.......\singt.qpf
.......\singt.qsf
.......\singt.qws
.......\singt.sim.rpt
.......\singt.tan.rpt
.......\singt.tan.summary
.......\singt.vhd
.......\singt.vwf
.......\sin_rom.mif
.......\db
sin_gnt
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