VeriHDL language editor with a four of seven light-emitting diode binary+

sxl\db\prev_cmp_sxl.asm.qmsg
...\..\prev_cmp_sxl.fit.qmsg
...\..\prev_cmp_sxl.map.qmsg
...\..\prev_cmp_sxl.qmsg
...\..\prev_cmp_sxl.sim.qmsg
...\..\prev_cmp_sxl.tan.qmsg
...\..\sxl.asm.qmsg
...\..\sxl.cbx.xml
...\..\sxl.cmp.cdb
...\..\sxl.cmp.hdb
...\..\sxl.cmp.logdb
...\..\sxl.cmp.rdb
...\..\sxl.cmp.tdb
...\..\sxl.cmp0.ddb
...\..\sxl.db_info
...\..\sxl.eco.cdb
...\..\sxl.eds_overflow
...\..\sxl.fit.qmsg
...\..\sxl.fnsim.cdb
...\..\sxl.fnsim.hdb
...\..\sxl.fnsim.qmsg
...\..\sxl.hier_info
...\..\sxl.hif
...\..\sxl.lpc.html
...\..\sxl.lpc.rdb
...\..\sxl.lpc.txt
...\..\sxl.map.cdb
...\..\sxl.map.hdb
...\..\sxl.map.logdb
...\..\sxl.map.qmsg
...\..\sxl.pre_map.cdb
...\..\sxl.pre_map.hdb
...\..\sxl.rpp.qmsg
...\..\sxl.rtlv.hdb
...\..\sxl.rtlv_sg.cdb
...\..\sxl.rtlv_sg_swap.cdb
...\..\sxl.sgate.rvd
...\..\sxl.sgate_sm.rvd
...\..\sxl.sgdiff.cdb
...\..\sxl.sgdiff.hdb
...\..\sxl.sim.hdb
...\..\sxl.sim.qmsg
...\..\sxl.sim.rdb
...\..\sxl.simfam
...\..\sxl.sim_ori.vwf
...\..\sxl.sld_design_entry.sci
...\..\sxl.sld_design_entry_dsc.sci
...\..\sxl.syn_hier_info
...\..\sxl.tan.qmsg
...\..\sxl.tis_db_list.ddb
...\incremental_db\compiled_partitions\sxl.root_partition.map.kpt
...\..............\README
...\sxl.asm.rpt
...\sxl.done
...\sxl.fit.rpt
...\sxl.fit.summary
...\sxl.flow.rpt
...\sxl.map.rpt
...\sxl.map.smsg
...\sxl.map.summary
...\sxl.pin
...\sxl.pof
...\sxl.qpf
...\sxl.qsf
...\sxl.sim.rpt
...\sxl.sof
...\sxl.tan.rpt
...\sxl.tan.summary
...\sxl.v
...\sxl.v.bak
...\sxl.vwf
...\incremental_db\compiled_partitions
...\db
...\incremental_db
sxl

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