verilog experiment: inputs and outputs are 4 to 2 8-bit hexadecimal number selector

vhdl4\lab4.cr.mti
.....\lab4.mpf
.....\lianxi4.bmp
.....\slec8.v
.....\slec_test.v
.....\vsim.wlf
.....\work\@_opt\vopt2jeeti
.....\....\.....\vopt634bti
.....\....\.....\vopt64ad9h
.....\....\.....\vopt9js8ti
.....\....\.....\vopt9kza9h
.....\....\.....\voptdwe478
.....\....\.....\voptg391ah
.....\....\.....\voptkjyy9h
.....\....\.....\voptkvjvq9
.....\....\.....\voptq3kt9h
.....\....\.....\voptqb9rq9
.....\....\.....\voptv35qsi
.....\....\.....\voptvw9mcv
.....\....\.....\_deps
.....\....\.....1\vopt22amdx
.....\....\......\vopt5izidx
.....\....\......\vopt92mfdx
.....\....\......\voptghy5ex
.....\....\......\voptjhj2yi
.....\....\......\voptq8vzgq
.....\....\......\voptyhkrdx
.....\....\......\_deps
.....\....\mux_8\_primary.dat
.....\....\.....\_primary.dbs
.....\....\.....\_primary.vhd
.....\....\test\_primary.dat
.....\....\....\_primary.dbs
.....\....\....\_primary.vhd
.....\....\_info
.....\....\_vmake
.....\....\@_opt
.....\....\@_opt1
.....\....\mux_8
.....\....\test
.....\....\_temp
.....\work
vhdl4

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