Analysis of a variety of video capture programs reviewed. On how to use CCD camera capture high-resolution, high-quality images, as well as FPGA-based embedded video image acquisition system realization method was studied. Used to camera mode+ decoder chip collection program for video decoder chip ADV7181B, realized the I2C bus configuration, ITU656 decoder, VGA display module design. The video capture controller has been designed in the Altera s CycloneII series FPGA (EP2C35) to achieve. The results showed that this design has a high speed, low cost, easy to integrate the advantages of

DE2_TV\AUDIO_DAC.v
......\db\add_sub_lkc.tdf
......\..\add_sub_mkc.tdf
......\..\altsyncram_drg1.tdf
......\..\altsyncram_h2c1.tdf
......\..\altsyncram_q0c1.tdf
......\..\alt_synch_pipe_rdb.tdf
......\..\alt_synch_pipe_vd8.tdf
......\..\alt_u_div_p1g.tdf
......\..\a_gray2bin_kdb.tdf
......\..\a_graycounter_egc.tdf
......\..\a_graycounter_fgc.tdf
......\..\a_graycounter_o96.tdf
......\..\cmpr_536.tdf
......\..\cmpr_ldc.tdf
......\..\cntr_hpf.tdf
......\..\dcfifo_iep1.tdf
......\..\DE2_TV.asm.qmsg
......\..\DE2_TV.asm.rdb
......\..\DE2_TV.asm_labs.ddb
......\..\DE2_TV.cbx.xml
......\..\DE2_TV.cmp.cbp
......\..\DE2_TV.cmp.cdb
......\..\DE2_TV.cmp.hdb
......\..\DE2_TV.cmp.kpt
......\..\DE2_TV.cmp.logdb
......\..\DE2_TV.cmp.rdb
......\..\DE2_TV.cmp.tdb
......\..\DE2_TV.cmp0.ddb
......\..\DE2_TV.cmp2.ddb
......\..\DE2_TV.db_info
......\..\DE2_TV.eco.cdb
......\..\DE2_TV.fit.qmsg
......\..\DE2_TV.hier_info
......\..\DE2_TV.hif
......\..\DE2_TV.lpc.html
......\..\DE2_TV.lpc.rdb
......\..\DE2_TV.lpc.txt
......\..\DE2_TV.map.cdb
......\..\DE2_TV.map.hdb
......\..\DE2_TV.map.logdb
......\..\DE2_TV.map.qmsg
......\..\DE2_TV.pre_map.cdb
......\..\DE2_TV.pre_map.hdb
......\..\DE2_TV.rom0_AUDIO_DAC_1ed7bfc5.hdl.mif
......\..\DE2_TV.rom0_I2C_AV_Config_fe53227f.hdl.mif
......\..\DE2_TV.rtlv.hdb
......\..\DE2_TV.rtlv_sg.cdb
......\..\DE2_TV.rtlv_sg_swap.cdb
......\..\DE2_TV.sgdiff.cdb
......\..\DE2_TV.sgdiff.hdb
......\..\DE2_TV.sld_design_entry.sci
......\..\DE2_TV.sld_design_entry_dsc.sci
......\..\DE2_TV.smart_action.txt
......\..\DE2_TV.smp_dump.txt
......\..\DE2_TV.syn_hier_info
......\..\DE2_TV.tan.qmsg
......\..\DE2_TV.tis_db_list.ddb
......\..\DE2_TV.tmw_info
......\..\ded_mult_ob91.tdf
......\..\dffpipe_b3c.tdf
......\..\dffpipe_kec.tdf
......\..\dffpipe_ngh.tdf
......\..\dffpipe_oe9.tdf
......\..\dffpipe_pe9.tdf
......\..\dffpipe_qe9.tdf
......\..\logic_util_heursitic.dat
......\..\lpm_divide_d6t.tdf
......\..\mult_add_4f74.tdf
......\..\prev_cmp_DE2_TV.asm.qmsg
......\..\prev_cmp_DE2_TV.fit.qmsg
......\..\prev_cmp_DE2_TV.map.qmsg
......\..\prev_cmp_DE2_TV.tan.qmsg
......\..\shift_taps_k0r.tdf
......\..\sign_div_unsign_3li.tdf
......\DE2_TV.asm.rpt
......\DE2_TV.done
......\DE2_TV.fit.rpt
......\DE2_TV.fit.smsg
......\DE2_TV.fit.summary
......\DE2_TV.flow.rpt
......\DE2_TV.map.rpt
......\DE2_TV.map.summary
......\DE2_TV.pin
......\DE2_TV.pof
......\DE2_TV.qpf
......\DE2_TV.qsf
......\DE2_TV.qws
......\DE2_TV.sof
......\DE2_TV.tan.rpt
......\DE2_TV.tan.summary
......\DE2_TV.v
......\DE2_TV_assignment_defaults.qdf
......\DIV.v
......\I2C_AV_Config.v
......\I2C_Controller.v
......\incremental_db\compiled_partitions\DE2_TV.root_partition.map.kpt
......\..............\README
......\ITU_656_Decoder.v
......\Line_Buffer.v

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