Our laboratory data, very helpful for learning FPGA, using the verilog language programming

FPGAyuandaima\Verilog代码\c10\10-2\mult.xco
.............\...........\...\....\mult.xco.!ut
.............\...........\...\....\mydds.xco
.............\...........\...\....\mydds.xco.!ut
.............\...........\...\....\square_syn.v
.............\...........\...\....\square_syn.v.!ut
.............\...........\...\...4\coastas_dds.v
.............\...........\...\....\coastas_dds.v.!ut
.............\...........\...\....\costas_lf.v
.............\...........\...\....\costas_lf.v.!ut
.............\...........\...\....\costas_loop.v
.............\...........\...\....\costas_loop.v.!ut
.............\...........\...\....\costas_lpf.v
.............\...........\...\....\costas_lpf.v.!ut
.............\...........\...\....\costas_mult.v
.............\...........\...\....\costas_mult.v.!ut
.............\...........\...\....\err_mult.v
.............\...........\...\....\err_mult.v.!ut
.............\...........\...\....\fir_lpf.xco
.............\...........\...\....\fir_lpf.xco.!ut
.............\...........\...\....\mult.xco
.............\...........\...\....\mult.xco.!ut
.............\...........\...\....\my_dds.xco
.............\...........\...\....\my_dds.xco.!ut
.............\...........\...\...6\dearly_sub.v
.............\...........\...\....\dearly_sub.v.!ut
.............\...........\...\....\dedds.v
.............\...........\...\....\dedds.v.!ut
.............\...........\...\....\delay_early_gate.v
.............\...........\...\....\delay_early_gate.v.!ut
.............\...........\...\....\de_mult.xco
.............\...........\...\....\de_mult.xco.!ut
.............\...........\...\....\eddds.xco
.............\...........\...\....\eddds.xco.!ut
.............\...........\...\....\iir.v
.............\...........\...\....\iir.v.!ut
.............\...........\...\....\iir1.v
.............\...........\...\....\iir1.v.!ut
.............\...........\...\...8\baker.v
.............\...........\...\....\baker.v.!ut
.............\...........\..1\11-10\div16.xco
.............\...........\...\.....\div16.xco.!ut
.............\...........\...\.....\fir_rls.v
.............\...........\...\.....\fir_rls.v.!ut
.............\...........\...\.....\rlsmult.xco
.............\...........\...\.....\rlsmult.xco.!ut
.............\...........\...\.....\shiftreg25.xco
.............\...........\...\.....\shiftreg25.xco.!ut
.............\...........\...\.....\shiftreg28.xco
.............\...........\...\.....\shiftreg28.xco.!ut
.............\...........\...\.....\shiftreg3.xco
.............\...........\...\.....\shiftreg3.xco.!ut
.............\...........\...\....2\dfe_filter.v
.............\...........\...\.....\dfe_filter.v.!ut
.............\...........\...\.....\dfe_mult.xco
.............\...........\...\.....\dfe_mult.xco.!ut
.............\...........\...\....4\aa_adder.xco
.............\...........\...\.....\aa_adder.xco.!ut
.............\...........\...\.....\aa_bram.xco
.............\...........\...\.....\aa_bram.xco.!ut
.............\...........\...\.....\aa_cmult.xco
.............\...........\...\.....\aa_cmult.xco.!ut
.............\...........\...\.....\ad_a.v
.............\...........\...\.....\ad_a.v.!ut
.............\...........\...\.....\shift16.xco
.............\...........\...\.....\shift16.xco.!ut
.............\...........\...\...2\fir_lms.v
.............\...........\...\....\fir_lms.v.!ut
.............\...........\...\...3\fir_pipline_lms.v
.............\...........\...\....\fir_pipline_lms.v.!ut
.............\...........\...\....\lmsmult.xco
.............\...........\...\....\lmsmult.xco.!ut
.............\...........\...\...5\mult.xco
.............\...........\...\....\mult.xco.!ut
.............\...........\...\....\shiftreg4.xco
.............\...........\...\....\shiftreg4.xco.!ut
.............\...........\...\....\sign_fir_lms.v
.............\...........\...\....\sign_fir_lms.v.!ut
.............\...........\...\...8\blockconnect.v
.............\...........\...\....\blockconnect.v.!ut
.............\...........\...\....\cmult.v
.............\...........\...\....\cmult.v.!ut
.............\...........\...\....\coe_updata.v
.............\....

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