Latches used for the programmable logic controller code, in fact, I do not quite understand, according to writing, there are strange No wonder, then

pll50.flow.rpt
pll50.map.rpt
pll50.map.summary
pll50.pin
pll50.pof
pll50.ppf
pll50.qpf
pll50.qsf
pll50.qws
pll50.sim.rpt
pll50.sof
pll50.tan.rpt
pll50.tan.summary
pll50.vhd
pll50.vwf
pll50_wave0.jpg
pll50_waveforms.html
db\pll50.asm.qmsg
..\pll50.cbx.xml
..\pll50.cmp.cdb
..\pll50.cmp.hdb
..\pll50.cmp.kpt
..\pll50.cmp.logdb
..\pll50.cmp.rdb
..\pll50.cmp.tdb
..\pll50.cmp0.ddb
..\pll50.dbp
..\pll50.db_info
..\pll50.eco.cdb
..\pll50.eds_overflow
..\pll50.fit.qmsg
..\pll50.hier_info
..\pll50.hif
..\pll50.map.cdb
..\pll50.map.hdb
..\pll50.map.logdb
..\pll50.map.qmsg
..\pll50.pre_map.cdb
..\pll50.pre_map.hdb
..\pll50.psp
..\pll50.rtlv.hdb
..\pll50.rtlv_sg.cdb
..\pll50.rtlv_sg_swap.cdb
..\pll50.sgdiff.cdb
..\pll50.sgdiff.hdb
..\pll50.signalprobe.cdb
..\pll50.sim.hdb
..\pll50.sim.qmsg
..\pll50.sim.rdb
..\pll50.sim.vwf
..\pll50.sld_design_entry.sci
..\pll50.sld_design_entry_dsc.sci
..\pll50.syn_hier_info
..\pll50.tan.qmsg
..\wed.zsf
pll50.asm.rpt
pll50.bsf
pll50.cmp
pll50.done
pll50.dpf
pll50.fit.rpt
pll50.fit.smsg
pll50.fit.summary
db

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