SPI IP core source code, including the two languages ​ ​ Verilog and VHDL source code

CoreSPI_eval
............\doc
............\...\CHANGES.txt
............\...\CoreSPI_DS.pdf
............\...\CoreSPI_RN.pdf
............\...\CoreSPI_UG.pdf
............\sim
............\...\mti_full
............\...\........\user
............\...\........\....\work_vhdl
............\...\........\....\.........\_info
............\...\........\....\.........\spi_master
............\...\........\....\.........\..........\_primary.dat
............\...\........\....\.........\..........\behv.dat
............\...\........\....\.........\..........\behv.asm
............\...\........\....\.........\spi_slave
............\...\........\....\.........\.........\_primary.dat
............\...\........\....\.........\.........\behv.dat
............\...\........\....\.........\.........\behv.asm
............\...\........\....\.........\corespi
............\...\........\....\.........\.......\_primary.dat
............\...\........\....\.........\.......\behv.dat
............\...\........\....\.........\.......\behv.asm
............\...\........\....\.........\tb_vhdl
............\...\........\....\.........\.......\_primary.dat
............\...\........\....\.........\.......\behv.dat
............\...\........\....\.........\.......\behv.asm
............\...\........\....\corespi_lib
............\...\........\....\...........\_info
............\...\........\....\...........\corespi_pkg
............\...\........\....\...........\...........\_primary.dat
............\...\........\....\...........\...........\_vhdl.asm
............\...\........\....\...........\...........\body.dat
............\...\........\....\...........\...........\body.asm
............\...\........\....\work_vlog
............\...\........\....\.........\_info
............\...\........\....\.........\spi_master
............\...\........\....\.........\..........\verilog.asm
............\...\........\....\.........\..........\_primary.dat
............\...\........\....\.........\spi_slave
............\...\........\....\.........\.........\verilog.asm
............\...\........\....\.........\.........\_primary.dat
............\...\........\....\.........\@c@o@r@e@s@p@i
............\...\........\....\.........\..............\_primary.vhd
............\...\........\....\.........\..............\verilog.asm
............\...\........\....\.........\..............\_primary.dat
............\...\........\....\.........\tb_vlog
............\...\........\....\.........\.......\_primary.vhd
............\...\........\....\.........\.......\verilog.asm
............\...\........\....\.........\.......\_primary.dat
............\...\........\....\compvhdl.do
............\...\........\....\compvlog.do
............\...\........\....\refreshvhdl.do
............\...\........\....\refreshvlog.do
............\...\........\....\wavetb.do
............\...\........\....\runvhdl.do
............\...\........\....\runvlog.do
............\...\mti_libero
............\...\..........\user
............\...\..........\....\work_vhdl
............\...\..........\....\.........\_info
............\...\..........\....\.........\spi_master
............\...\..........\....\.........\..........\_primary.dat
............\...\..........\....\.........\..........\behv.dat
............\...\..........\....\.........\..........\behv.psm
............\...\..........\....\.........\spi_slave
............\...\..........\....\.........\.........\_primary.dat
............\...\..........\....\.........\.........\behv.dat
............\...\..........\....\.........\.........\behv.psm
............\...\..........\....\.........\corespi
............\...\..........\....\.........\.......\_primary.dat
............\...\..........\....\.........\.......\behv.dat
............\...\..........\....\.........\.......\behv.psm
............\...\..........\....\.........\tb_vhdl
............\...\..........\....\.........\.......\_primary.dat
............\...\..........\....\.........\.......\behv.dat
............\...\..........\....\.........\.......\behv.psm
............\...\..........\....\corespi_lib
............\...\..........\....\......

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