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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 5kb
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  • Author :your*****
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Introduction - If you have any usage issues, please Google them yourself
1, the search for the data stream signal in the frame synchronization word and frame synchronization flag is given. 2, the system works after the start of 3 consecutive times to confirm the frame synchronization word into the locked state after the output frame sync flag. 3, in the locked state, such as 3 consecutive incorrect frame synchronization word, the output frame sync flag is invalid, the system re-entering the search state otherwise continue to output a valid frame sync flag.
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tongbu.doc
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