Hardware Description Language(HDL)is an advanced electronic designmethod．After HDL was put into use，it has draw great attention and gained popularity．The design used Verilog HDL and Schematic for entry tools having good effect in the system design，Meanwhile，it adopted the core provided by Xilinx／nc. improving the design efficiency．The whole design which is implemented inXC2S600E device relied on ISE and advanced hierarchy design mind．Furthermore，it is simulated and verified．The frequency attains to 40.64MHz．this paper aims at demonstration the applying FPGA to FFT signal processing can complete 256 pointsFFT.

synth_fft\and_gates.vhd
.........\baseindex.vhd
.........\but.vhd
.........\butter_lib.vhd
.........\comm.txt
.........\control2.vhd
.........\controller.vhd
.........\counter.vhd
.........\cycles_but.vhd
.........\dff.vhd
.........\divide.vhd
.........\FLOAT2.PIF
.........\FLOAT_RE.TXT
.........\IEEE_TO_.PIF
.........\ioadd.vhd
.........\iod_staged.vhd
.........\lblock.vhd
.........\mult.vhd
.........\multiply.vhd
.........\mux_add.vhd
.........\mux_but.vhd
.........\negate.vhd
.........\normalize.vhd
.........\out_result.vhd
.........\print.vhd
.........\ram.vhd
.........\ram_shift.vhd
.........\rblock.vhd
.........\result.txt
.........\rom.vhd
.........\romadd_gen.vhd
.........\rom_ram.vhd
.........\shift2.vhd
.........\simili.lst
.........\stage.vhd
.........\subtractor.vhd
.........\summer.vhd
.........\swap.vhd
.........\synth_main.vhd
.........\synth_test.vhd
.........\......fft\and_gates.vhd
.........\.........\baseindex.vhd
.........\.........\but.vhd
.........\.........\butter_lib.vhd
.........\.........\comm.txt
.........\.........\control2.vhd
.........\.........\controller.vhd
.........\.........\counter.vhd
.........\.........\cycles_but.vhd
.........\.........\dff.vhd
.........\.........\divide.vhd
.........\.........\FLOAT2.PIF
.........\.........\FLOAT_RE.TXT
.........\.........\IEEE_TO_.PIF
.........\.........\ioadd.vhd
.........\.........\iod_staged.vhd
.........\.........\lblock.vhd
.........\.........\mult.vhd
.........\.........\multiply.vhd
.........\.........\mux_add.vhd
.........\.........\mux_but.vhd
.........\.........\negate.vhd
.........\.........\normalize.vhd
.........\.........\out_result.vhd
.........\.........\print.vhd
.........\.........\ram.vhd
.........\.........\ram_shift.vhd
.........\.........\rblock.vhd
.........\.........\result.txt
.........\.........\rom.vhd
.........\.........\romadd_gen.vhd
.........\.........\rom_ram.vhd
.........\.........\shift2.vhd
.........\.........\simili.lst
.........\.........\stage.vhd
.........\.........\subtractor.vhd
.........\.........\summer.vhd
.........\.........\swap.vhd
.........\.........\synth_main.vhd
.........\.........\synth_test.vhd
.........\synth_fft
synth_fft

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