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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 8kb
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  • Author :赵****
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Introduction - If you have any usage issues, please Google them yourself
General Digital Clock Clock setting with Switch – Use Key_up and Key_down key to change the number – Use Key_right and Key_left key to change the position – Use set key to start Clock Alarm Function – Use Alarm key to set Alarm clock Alarm On/Off Function Stop Watch(1/100 sec) Function – Use SW_Start/Stop key to start and stop Stop Watch count – Use SW_Reset key to reset Stop Watch count
Packet file list
(Preview for download)
rtl\alarm.vhd
...\clk_div.vhd
...\clock.vhd
...\control.vhd
...\C_Seg_Driver.vhd
...\dip_control.vhd
...\key.vhd
...\sg_disp.vhd
...\stop_watch.vhd
...\TOP.vhd
rtl
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