Introduction - If you have any usage issues, please Google them yourself
This paper describes the JTAG standard and SoC debugging technology, research-based JTAG debugging multi-core SoC structure, optimized multi-core SoC debugging a fully compliant structure, the JTAG controller can be configured into a variety of interconnect models in order to achieve a single-core or multi-core SoC debugging then IEEEl 149.1 standard structured on the basis of improved, expanded instruction set and registers, to achieve standards-based SoC JTAG debug system Finally, a functional test system SoC debugging and performance analysis The test results show that the implementation of SoC debug system debugging tools than the existing similar in function and performance are improved obviously.