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example7

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 403kb
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  • Author :黄***
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Introduction - If you have any usage issues, please Google them yourself
Instances of traffic lights at a crossroads, with the hardware description language (vhdl), prepared
Packet file list
(Preview for download)
example7\jtd.cdf
........\jtd.done
........\jtd.dpf
........\jtd.fit.smsg
........\jtd.fit.summary
........\jtd.map.summary
........\jtd.pin
........\jtd.pof
........\jtd.qpf
........\jtd.qsf
........\jtd.qws
........\jtd.tan.summary
........\jtd.vhd
........\jtd_assignment_defaults.qdf
........\db\jtd.db_info
........\..\jtd.map.qmsg
........\..\jtd.cmp.rdb
........\..\jtd.sld_design_entry.sci
........\..\jtd.cbx.xml
........\..\jtd.hif
........\..\logic_util_heursitic.dat
........\..\jtd.hier_info
........\..\jtd.rtlv_sg.cdb
........\..\jtd.smart_action.txt
........\..\jtd.rtlv_sg_swap.cdb
........\..\jtd.rtlv.hdb
........\..\jtd.lpc.txt
........\..\prev_cmp_jtd.qmsg
........\..\jtd.lpc.html
........\..\jtd.pre_map.hdb
........\..\jtd.lpc.rdb
........\..\jtd.pre_map.cdb
........\..\jtd.map.logdb
........\..\jtd.sgdiff.cdb
........\..\jtd.sgdiff.hdb
........\..\jtd.sld_design_entry_dsc.sci
........\..\jtd.syn_hier_info
........\..\jtd.fit.qmsg
........\..\jtd.cmp.logdb
........\..\jtd.amm.cdb
........\..\jtd.asm.qmsg
........\..\jtd.map.cdb
........\..\jtd.map.hdb
........\..\jtd.cmp.kpt
........\..\jtd.asm_labs.ddb
........\..\jtd.asm.rdb
........\..\jtd.tis_db_list.ddb
........\..\jtd.cmp.cdb
........\..\jtd.cmp.hdb
........\..\jtd.idb.cdb
........\..\jtd.tan.qmsg
........\..\jtd.cmp.tdb
........\..\jtd.cmp0.ddb
........\incremental_db\compiled_partitions\jtd.db_info
........\..............\...................\jtd.root_partition.map.kpt
........\..............\README
........\jtd.map.rpt
........\jtd.fit.rpt
........\jtd.asm.rpt
........\jtd.tan.rpt
........\jtd.flow.rpt
........\incremental_db\compiled_partitions
........\db
........\incremental_db
example7
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