this is a uart verilog HDL design code

UART\altlvds_rx0.v
....\altlvds_rx0_bb.v
....\altlvds_rx1.v
....\altlvds_rx1_bb.v
....\cmp_state.ini
....\db\cntr_ea7.tdf
....\..\cntr_qu7.tdf
....\..\lvds_rx_j2c.tdf
....\..\rcvr.asm.qmsg
....\..\rcvr.cmp.cdb
....\..\rcvr.cmp.ddb
....\..\rcvr.cmp.hdb
....\..\rcvr.cmp.rdb
....\..\rcvr.cmp.tdb
....\..\rcvr.cmp0.ddb
....\..\rcvr.db_info
....\..\rcvr.eco.cdb
....\..\rcvr.fit.qmsg
....\..\rcvr.hier_info
....\..\rcvr.hif
....\..\rcvr.icc
....\..\rcvr.map.cdb
....\..\rcvr.map.hdb
....\..\rcvr.map.qmsg
....\..\rcvr.pre_map.cdb
....\..\rcvr.pre_map.hdb
....\..\rcvr.psp
....\..\rcvr.rtlv.hdb
....\..\rcvr.rtlv_sg.cdb
....\..\rcvr.rtlv_sg_swap.cdb
....\..\rcvr.sgdiff.cdb
....\..\rcvr.sgdiff.hdb
....\..\rcvr.signalprobe.cdb
....\..\rcvr.sld_design_entry.sci
....\..\rcvr.sld_design_entry_dsc.sci
....\..\rcvr.syn_hier_info
....\..\rcvr.tan.qmsg
....\..\shift_reg_4n5.tdf
....\..\Test.asm.qmsg
....\..\Test.cbx.xml
....\..\Test.cmp.cdb
....\..\Test.cmp.hdb
....\..\Test.cmp.rdb
....\..\Test.cmp.tdb
....\..\Test.cmp0.ddb
....\..\Test.db_info
....\..\Test.eco.cdb
....\..\Test.eds_overflow
....\..\Test.fit.qmsg
....\..\Test.hier_info
....\..\Test.hif
....\..\Test.map.cdb
....\..\Test.map.hdb
....\..\Test.map.qmsg
....\..\Test.pre_map.cdb
....\..\Test.pre_map.hdb
....\..\Test.psp
....\..\Test.rtlv.hdb
....\..\Test.rtlv_sg.cdb
....\..\Test.rtlv_sg_swap.cdb
....\..\Test.sgdiff.cdb
....\..\Test.sgdiff.hdb
....\..\Test.signalprobe.cdb
....\..\Test.sim.hdb
....\..\Test.sim.qmsg
....\..\Test.sim.rdb
....\..\Test.sld_design_entry.sci
....\..\Test.sld_design_entry_dsc.sci
....\..\Test.syn_hier_info
....\..\Test.tan.qmsg
....\..\test2.asm.qmsg
....\..\test2.cmp.cdb
....\..\test2.cmp.ddb
....\..\test2.cmp.hdb
....\..\test2.cmp.rdb
....\..\test2.cmp.tdb
....\..\test2.cmp0.ddb
....\..\test2.db_info
....\..\test2.eco.cdb
....\..\test2.eds_overflow
....\..\test2.fit.qmsg
....\..\test2.hier_info
....\..\test2.hif
....\..\test2.icc
....\..\test2.map.cdb
....\..\test2.map.hdb
....\..\test2.map.qmsg
....\..\test2.pre_map.cdb
....\..\test2.pre_map.hdb
....\..\test2.psp
....\..\test2.rtlv.hdb
....\..\test2.rtlv_sg.cdb
....\..\test2.rtlv_sg_swap.cdb
....\..\test2.sgdiff.cdb
....\..\test2.sgdiff.hdb
....\..\test2.signalprobe.cdb
....\..\test2.sim.hdb
....\..\test2.sim.qmsg
....\..\test2.sim.rdb
....\..\test2.sld_design_entry.sci

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