Their series a frequency counter, verilog language written with the digital display of the square wave frequency, measurement range is 0.1hz ~ 9999999hz, high stability of the square wave test.

cnt.v
con_cnt.v
dout.v
gate.v
INT_sig.v
lanch.v
Selchansheng.v
top.v
clk_x.v
ourdream_shiti\clk_x.v
..............\clk_x.v.bak
..............\cnt.v
..............\cnt.v.bak
..............\con_cnt.v
..............\con_cnt.v.bak
..............\db\logic_util_heursitic.dat
..............\..\prev_cmp_top.qmsg
..............\..\top.amm.cdb
..............\..\top.asm.qmsg
..............\..\top.asm.rdb
..............\..\top.asm_labs.ddb
..............\..\top.cbx.xml
..............\..\top.cmp.bpm
..............\..\top.cmp.cbp
..............\..\top.cmp.cdb
..............\..\top.cmp.hdb
..............\..\top.cmp.kpt
..............\..\top.cmp.logdb
..............\..\top.cmp.rdb
..............\..\top.cmp.tdb
..............\..\top.cmp0.ddb
..............\..\top.cmp2.ddb
..............\..\top.cmp_merge.kpt
..............\..\top.db_info
..............\..\top.eda.qmsg
..............\..\top.fit.qmsg
..............\..\top.hier_info
..............\..\top.hif
..............\..\top.idb.cdb
..............\..\top.lpc.html
..............\..\top.lpc.rdb
..............\..\top.lpc.txt
..............\..\top.map.bpm
..............\..\top.map.cbp
..............\..\top.map.cdb
..............\..\top.map.hdb
..............\..\top.map.kpt
..............\..\top.map.logdb
..............\..\top.map.qmsg
..............\..\top.map_bb.cdb
..............\..\top.map_bb.hdb
..............\..\top.map_bb.logdb
..............\..\top.pre_map.cdb
..............\..\top.pre_map.hdb
..............\..\top.rtlv.hdb
..............\..\top.rtlv_sg.cdb
..............\..\top.rtlv_sg_swap.cdb
..............\..\top.sgdiff.cdb
..............\..\top.sgdiff.hdb
..............\..\top.sld_design_entry.sci
..............\..\top.sld_design_entry_dsc.sci
..............\..\top.smart_action.txt
..............\..\top.syn_hier_info
..............\..\top.tan.qmsg
..............\..\top.tis_db_list.ddb
..............\..\top.tmw_info
..............\dout.v
..............\dout.v.bak
..............\gate.v
..............\gate.v.bak
..............\incremental_db\compiled_partitions\top.db_info
..............\..............\...................\top.root_partition.cmp.cdb
..............\..............\...................\top.root_partition.cmp.dfp
..............\..............\...................\top.root_partition.cmp.hdb
..............\..............\...................\top.root_partition.cmp.kpt
..............\..............\...................\top.root_partition.cmp.logdb
..............\..............\...................\top.root_partition.cmp.rcfdb
..............\..............\...................\top.root_partition.cmp.re.rcfdb
..............\..............\...................\top.root_partition.map.cdb
..............\..............\...................\top.root_partition.map.dpi
..............\..............\...................\top.root_partition.map.hdb
..............\..............\...................\top.root_partition.map.kpt
..............\..............\README
..............\INT_sig.v
..............\INT_sig.v.bak
..............\lanch.v
..............\lanch.v.bak
..............\Selchansheng.v
..............\Selchansheng.v.bak
..............\simulation\modelsim\modelsim.ini
..............\..........\........\msim_transcript
..............\..........\........\rtl_work\@i@n@t_sig\verilog.prw
..............\..........\........\........\..........\verilog.psm
..............\..........\........\........\..........\_primary.dat
..............\..........\........\........\..........\_primary.dbs
..............\..........\........\........\..........\_primary.vhd
..............\..........\........\........\.selchansheng\verilog.prw
..............\..........\........\........\.............\verilog.psm
..............\..........\........\........\.............\_primary.dat
..............\..........\........\........\.............\_primary.dbs

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