Language described by verilog MIPS 5-stage pipeline.

pipelined-mips-cpu\Adder.v
..................\ALU.v
..................\ALU_Control.v
..................\Control.v
..................\Data_Memory.v
..................\Equal.v
..................\EX_MEM.v
..................\Forwarding.v
..................\Hazard_Detection.v
..................\ID_EX.v
..................\IF_ID.v
..................\Instr_Memory.v
..................\MEM_WB.v
..................\MUX_10bit.v
..................\MUX_2x32bit.v
..................\MUX_3x32bit.v
..................\MUX_5bit.v
..................\PC.v
..................\Pipelined_CPU.v
..................\Register_File.v
..................\Sign_Extend.v
..................\Testbench.v
pipelined-mips-cpu

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