quatuasII the practice test code, this information can self-learning and enhance self-confidence

text1\db\logic_util_heursitic.dat
.....\..\prev_cmp_text1.qmsg
.....\..\text1.amm.cdb
.....\..\text1.analyze_file.qmsg
.....\..\text1.asm.qmsg
.....\..\text1.asm.rdb
.....\..\text1.cbx.xml
.....\..\text1.cmp.cdb
.....\..\text1.cmp.hdb
.....\..\text1.cmp.kpt
.....\..\text1.cmp.logdb
.....\..\text1.cmp.rdb
.....\..\text1.cmp0.ddb
.....\..\text1.db_info
.....\..\text1.eda.qmsg
.....\..\text1.fit.qmsg
.....\..\text1.hier_info
.....\..\text1.hif
.....\..\text1.idb.cdb
.....\..\text1.lpc.html
.....\..\text1.lpc.rdb
.....\..\text1.lpc.txt
.....\..\text1.map.cdb
.....\..\text1.map.hdb
.....\..\text1.map.logdb
.....\..\text1.map.qmsg
.....\..\text1.pre_map.cdb
.....\..\text1.pre_map.hdb
.....\..\text1.rpp.qmsg
.....\..\text1.rtlv.hdb
.....\..\text1.rtlv_sg.cdb
.....\..\text1.rtlv_sg_swap.cdb
.....\..\text1.sgate.rvd
.....\..\text1.sgate_sm.rvd
.....\..\text1.sgdiff.cdb
.....\..\text1.sgdiff.hdb
.....\..\text1.sld_design_entry.sci
.....\..\text1.sld_design_entry_dsc.sci
.....\..\text1.smart_action.txt
.....\..\text1.syn_hier_info
.....\..\text1.tan.qmsg
.....\..\text1.tis_db_list.ddb
.....\..\text1.tmw_info
.....\incremental_db\compiled_partitions\text1.db_info
.....\..............\...................\text1.root_partition.map.kpt
.....\..............\README
.....\simulation\modelsim\gate_work\text1\verilog.prw
.....\..........\........\.........\.....\verilog.psm
.....\..........\........\.........\.....\_primary.dat
.....\..........\........\.........\.....\_primary.dbs
.....\..........\........\.........\.....\_primary.vhd
.....\..........\........\.........\....._vlg_tst\verilog.prw
.....\..........\........\.........\.............\verilog.psm
.....\..........\........\.........\.............\_primary.dat
.....\..........\........\.........\.............\_primary.dbs
.....\..........\........\.........\.............\_primary.vhd
.....\..........\........\.........\_info
.....\..........\........\.........\_vmake
.....\..........\........\modelsim.ini
.....\..........\........\msim_transcript
.....\..........\........\rtl_work\text1\verilog.prw
.....\..........\........\........\.....\verilog.psm
.....\..........\........\........\.....\_primary.dat
.....\..........\........\........\.....\_primary.dbs
.....\..........\........\........\.....\_primary.vhd
.....\..........\........\........\....._vlg_tst\verilog.prw
.....\..........\........\........\.............\verilog.psm
.....\..........\........\........\.............\_primary.dat
.....\..........\........\........\.............\_primary.dbs
.....\..........\........\........\.............\_primary.vhd
.....\..........\........\........\_info
.....\..........\........\........\_vmake
.....\..........\........\text1.sft
.....\..........\........\text1.vo
.....\..........\........\text1.vt
.....\..........\........\text1.vt.bak
.....\..........\........\text1_modelsim.xrf
.....\..........\........\text1_run_msim_gate_verilog.do
.....\..........\........\text1_run_msim_rtl_verilog.do
.....\..........\........\text1_run_msim_rtl_verilog.do.bak
.....\..........\........\text1_run_msim_rtl_verilog.do.bak1
.....\..........\........\text1_run_msim_rtl_verilog.do.bak2
.....\..........\........\text1_run_msim_rtl_verilog.do.bak3
.....\..........\........\text1_run_msim_rtl_verilog.do.bak4
.....\..........\........\text1_run_msim_rtl_verilog.do.bak5
.....\..........\........\text1_run_msim_rtl_verilog.do.bak6
.....\..........\........\text1_v.sdo
.....\..........\........\text1_v.sdo_typ.csd
.....\..........\........\vsim.wlf
.....\text1.asm.rpt
.....\text1.done
.....\text1.eda.rpt
.....\text1.fit.rpt
.....\text1.fit.smsg
.....\text1.fit.summary
.....\text1.flow.rpt
.....\text1.map.rpt
.....\text1.map.summary
.....\text1.pin
.....\text1.qpf

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