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FPGA_UART
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VHDL-FPGA-Verilog
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Update : 2012-11-26
Size : 5.75mb
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Author :
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Introduction - If you have any usage issues, please Google them yourself
Reedit
Which is referred to the UART VHDL design of the classic examples, and there are detailed explanation and analysis for the serial port for FPGA development.
Packet file list
(Preview for download)
FPGA_UART\SAVE2006-5-27_22-35-17.TXT
.........\SAVE2006-5-29_23-28-32.TXT
.........\sscom.ini
.........\SSCOM32.EXE
.........\基于VerilogHDL的UARTIP的设计.pdf
.........\基于Verilog_HDL的UART串行通讯模块设计及仿真.pdf
.........\CODE\PCM编解码器的软件实现.pdf
.........\....\基于FPGA的PCM帧同步检测及告警电路的设计.pdf
.........\....\基于FPGA的PCM编码器与解码器的设计与实现.pdf
.........\....\基于FPGA的可编程PCM采编器的实现.pdf
.........\....\基于FPGA的小数分频器的实现.pdf
.........\....\基于FPGA的数字通信系统帧同步电路设计.pdf
.........\....\基于VerilogHDL的PCM采编器设计与实现.pdf
.........\....\基于帧同步问题的一堂精品课设计.pdf
.........\....\uart\具有中断管理功能的多UART控制器设计.pdf
.........\....\....\基于ASIC_SoC的UART核的设计.kdh
.........\....\....\基于FPGA的UARTIP核设计与实现.pdf
.........\....\....\基于FPGA的简化UART电路设计.pdf
.........\....\....\基于VerilogHDL的UARTIP的设计.pdf
.........\....\....\基于Verilog_HDL的UART串行通讯模块设计及仿真.pdf
.........\....\....\基于有限状态机实现全双工可编程UART.pdf
.........\FPGA_UART_DRIVER\asm.h
.........\................\config.h
.........\................\garfield.h
.........\................\gpio.h
.........\................\HA_print.c
.........\................\head_gfd.s
.........\................\heap.s
.........\................\intc.H
.........\................\int_gfd.s
.........\................\int_vec_handler.c
.........\................\retarget.c
.........\................\scat_crremap.scf
.........\................\stack.s
.........\................\system.c
.........\................\system.h
.........\................\typedef.h
.........\................\uart.c
.........\................\uart.h
.........\................\fpga_uart\fpga_uart.mcp
.........\................\.........\........._Data\CWSettingsWindows.stg
.........\................\.........\..............\Debug\TargetDataWindows.tdt
.........\................\.........\..............\.....Rel\fpga_uart.axf
.........\................\.........\..............\........\TargetDataWindows.tdt
.........\................\.........\..............\........\ObjectCode\head_gfd.o
.........\................\.........\..............\........\..........\int_gfd.o
.........\................\.........\..............\........\..........\int_vec_handler.o
.........\................\.........\..............\........\..........\retarget.o
.........\................\.........\..............\........\..........\system.o
.........\................\.........\..............\........\..........\uart.o
.........\................\.........\..............\Release\TargetDataWindows.tdt
.........\VERILOG_CODE\fpga_top.qsf
.........\............\代码说明.txt
.........\............\proj\cmp_state.ini
.........\............\....\fpga_top.asm.rpt
.........\............\....\fpga_top.cdf
.........\............\....\fpga_top.done
.........\............\....\fpga_top.fit.eqn
.........\............\....\fpga_top.fit.rpt
.........\............\....\fpga_top.flow.rpt
.........\............\....\fpga_top.hexout
.........\............\....\fpga_top.map.eqn
.........\............\....\fpga_top.map.rpt
.........\............\....\fpga_top.pin
.........\............\....\fpga_top.pof
.........\............\....\fpga_top.prd
.........\............\....\fpga_top.prj
.........\............\....\fpga_top.qpf
.........\............\....\fpga_top.qsf
.........\............\....\fpga_top.qws
.........\............\....\fpga_top.sim.rpt
.........\............\....\fpga_top.sof
.........\............\....\fpga_top.tan.rpt
.........\............\....\fpga_top.tan.summary
.........\............\....\fpga_top_assignment_defaults.qdf
.........\............\....\output.pof
.........\............\....\output_file.pof
.........\............\....\db\fpga_top.db_info
.........\............\....\..\fpga_top.eco.cdb
.........\............\....\..\fpga_top.sld_design_entry.sci
.........\............\....\..\fpga_top_cmp.qrpt
.........\............\....\..\fpga_top_hier_info
.........\............\....\..\fpga_top_sim.qrpt
.........\............\....\..\fpga_
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