ram code in VHDL with its test code

RAM\SRAM\MEM_TB.fdo
...\....\MEM_TB.udo
...\....\MEM_TB_wave.fdo
...\....\SRAM.cmd_log
...\....\SRAM.ise
...\....\SRAM.lso
...\....\SRAM.ngc
...\....\SRAM.ngr
...\....\SRAM.ntrc_log
...\....\SRAM.prj
...\....\SRAM.restore
...\....\SRAM.stx
...\....\SRAM.syr
...\....\sram.vhd
...\....\SRAM.xst
...\....\SRAM_summary.html
...\....\sram_test.vhd
...\....\SRAM_vhdl.prj
...\....\SRAM_xst.xrpt
...\....\transcript
...\....\vsim.wlf
...\....\work\cfg_tb\_primary.dat
...\....\....\......\_vhdl.asm
...\....\....\mem_tb\tb.asm
...\....\....\......\tb.dat
...\....\....\......\_primary.dat
...\....\....\sram\behav.asm
...\....\....\....\behav.dat
...\....\....\....\_primary.dat
...\....\....\_info
...\....\xst\dump.xst\SRAM.prj\ntrc.scr
...\....\...\work\hdllib.ref
...\....\...\....\hdpdeps.ref
...\....\...\....\sub00\vhpl00.vho
...\....\...\....\.....\vhpl01.vho
...\....\_xmsgs\xst.xmsgs
...\....\xst\dump.xst\SRAM.prj\ngx\notopt
...\....\...\........\........\...\opt
...\....\...\........\........\ngx
...\....\...\........\SRAM.prj
...\....\...\work\sub00
...\....\SRAM_xdb\tmp
...\....\work\cfg_tb
...\....\....\mem_tb
...\....\....\sram
...\....\xst\dump.xst
...\....\...\projnav.tmp
...\....\...\work
...\....\SRAM_xdb
...\....\work
...\....\xst
...\....\_xmsgs
...\SRAM
RAM

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