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AnalizatorAndCounter

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 584kb
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  • Author :A*****
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VHDL counter project fo Altera DE2 Development Board
Packet file list
(Preview for download)
AnalizatorAndCounter\.sopc_builder\install.ptf
....................\CODER.bsf
....................\coder.tdf
....................\CODER_8_3.bsf
....................\cpu_0.ocp
....................\cpu_0.v
....................\cpu_0.vo
....................\cpu_0_bht_ram.mif
....................\cpu_0_dc_tag_ram.mif
....................\cpu_0_ext_trace_pll_module.v
....................\cpu_0_ic_tag_ram.mif
....................\cpu_0_jtag_debug_module.v
....................\cpu_0_jtag_debug_module_wrapper.v
....................\cpu_0_mult_cell.v
....................\cpu_0_ociram_default_contents.mif
....................\cpu_0_rf_ram_a.mif
....................\cpu_0_rf_ram_b.mif
....................\cpu_0_test_bench.v
....................\db\cntr_2rg.tdf
....................\..\cntr_j3i.tdf
....................\..\cntr_n3i.tdf
....................\..\cntr_pfh.tdf
....................\..\cntr_upj.tdf
....................\..\my_de2_project.db_info
....................\..\my_de2_project.eco.cdb
....................\..\my_de2_project.sld_design_entry.sci
....................\lcd_16207_0.v
....................\LCD_Controller.bsf
....................\LCD_TEST.bsf
....................\lpm_counter0.bsf
....................\lpm_counter0.cmp
....................\lpm_counter0.inc
....................\lpm_counter0.vhd
....................\lpm_counter1.bsf
....................\lpm_counter1.cmp
....................\lpm_counter1.inc
....................\lpm_counter1.vhd
....................\my_de2_project.asm.rpt
....................\my_de2_project.bdf
....................\my_de2_project.cdf
....................\my_de2_project.done
....................\my_de2_project.dpf
....................\my_de2_project.fit.rpt
....................\my_de2_project.fit.summary
....................\my_de2_project.flow.rpt
....................\my_de2_project.map.rpt
....................\my_de2_project.map.summary
....................\my_de2_project.merge.rpt
....................\my_de2_project.pin
....................\my_de2_project.pof
....................\my_de2_project.qpf
....................\my_de2_project.qsf
....................\my_de2_project.qws
....................\my_de2_project.sof
....................\my_de2_project.tan.rpt
....................\my_de2_project.tan.summary
....................\observer.bsf
....................\observer.ptf
....................\observer.ptf.bak
....................\observer.v
....................\observer_generation_script
....................\observer_log.txt
....................\observer_setup_quartus.tcl
....................\..........im\cfi_flash_0.dat
....................\............\contents_file_warning.txt
....................\............\cpu_0_bht_ram.dat
....................\............\cpu_0_bht_ram.hex
....................\............\cpu_0_dc_tag_ram.dat
....................\............\cpu_0_dc_tag_ram.hex
....................\............\cpu_0_ic_tag_ram.dat
....................\............\cpu_0_ic_tag_ram.hex
....................\............\cpu_0_ociram_default_contents.dat
....................\............\cpu_0_ociram_default_contents.hex
....................\............\cpu_0_rf_ram_a.dat
....................\............\cpu_0_rf_ram_a.hex
....................\............\cpu_0_rf_ram_b.dat
....................\............\cpu_0_rf_ram_b.hex
....................\............\create_observer_project.do
....................\............\list_presets.do
....................\............\modelsim.tcl
....................\............\setup_sim.do
....................\............\virtuals.do
....................\............\wave_presets.do
....................\pio_0.v
....................\RS.bdf
....................\RS.bsf
....................\software\blank_project_0_syslib\.cdtbuild
....................\........\......................\.cdtproject
....................\........\......................\.project
....................\........\......................\system.stf
....................\........\......................_0\.cdtbuild
....................\........\....................
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