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VHDL-FPGA-Verilog List Page 9

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[VHDL-FPGA-Verilogencryptionmethod.Rar

Description: FPGA encryption methods for those who need to encrypt their VHDL source code in a way, very useful
Platform: Windows_Unix | Size: 183KB | Author: taoweijiong | Hits: 181

[VHDL-FPGA-Verilogpn_code

Description: coefficient of the four scrambler generator, and every four scrambler have triggered a string conversion and the trigger signal can be used to trigger 4b/5b coding signal. Verilog procedures, with test procedures
Platform: C++ | Size: 35KB | Author: goalig | Hits: 45

[VHDL-FPGA-Verilogfen

Description: Verilog, 4,5 dividers, five dividers ratio of 3:2
Platform: Visual C++ | Size: 150KB | Author: goalig | Hits: 64

[VHDL-FPGA-Veriloginface

Description: an interface to the control board CPLD logic circuit design process.
Platform: MultiPlatform | Size: 4KB | Author: oyanifont | Hits: 22

[VHDL-FPGA-VerilogKey16

Description: 4x4 keyboard module. The documents include ordinary keyboard design program descriptions and procedures related to the original.
Platform: C-C++ | Size: 49KB | Author: 波波 | Hits: 87

[VHDL-FPGA-Veriloghdb3decoder

Description: I do view on the VHDL design options for the CPLD or FPGA to achieve HDB3 code
Platform: TEXT | Size: 117KB | Author: wangweivivian | Hits: 112

[VHDL-FPGA-VerilogFPGA-baseddirectdigitalsynthesisdesign.Rar

Description: a use FLEX10-chip RAM resources, in accordance with DDS principle, design sinusoidal signal generated by the top-level functional modules and schematics; 2, the experimental board TLC7259 converters, will be a sinusoidal signal, the D/A conversion, after filtering through the ME5534 oscilloscope observation; 3, the output waveform requirements : the input clock frequency of 16KHz, sine wave output resolution of 1Hz; the input clock frequency of 4MHz, the sine wave output resolution of 256Hz; 4, RS232C communications, FPGA and PC serial communications between in order to achieve PC-frequency control characters, the realization of sine wave output frequency control.
Platform: Windows_Unix | Size: 21KB | Author: cymail | Hits: 303

[VHDL-FPGA-VerilogVHDLsetprocedures.Zip

Description: I am learning more systematic series of practical VHDL source Giant
Platform: TEXT | Size: 13KB | Author: lijian528 | Hits: 69

[VHDL-FPGA-Verilogalu

Description: Verilog modules prepared by the ALU
Platform: MultiPlatform | Size: 1KB | Author: liululu | Hits: 46

[VHDL-FPGA-Verilogpipe

Description: Verilog modules prepared by the Pipeline
Platform: MultiPlatform | Size: 5KB | Author: liululu | Hits: 79

[VHDL-FPGA-Verilogpercent

Description: Verilog prepared by calculating the percentage module
Platform: MultiPlatform | Size: 91KB | Author: liululu | Hits: 10

[VHDL-FPGA-Verilog cuart

Description: verilog programme of serial port
Platform: MultiPlatform | Size: 5KB | Author: liululu | Hits: 62
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