[VHDL-FPGA-Verilog] jtag0

Description: vhdl the procedures used to prepare the jtag interface procedures, which some of them did not materialize, hope someone can help perfect!
Platform: WINDOWS | Size: 84KB | Author: mabin21 | Hits: 28

[VHDL-FPGA-Verilog] ref-ddr-sdram-vhdl

Description: Compiles DDR SDRAM Controller with VHDL the source code
Platform: Windows_Unix | Size: 1007KB | Author: bao.shenghua1 | Hits: 156

[VHDL-FPGA-Verilog] Vhdl

Description: This is about a V H D L article
Platform: WINDOWS | Size: 405KB | Author: zhu408.student | Hits: 15

[VHDL-FPGA-Verilog] sdram_vhdl_lattice

Description: Sound code of Lattice Sdram Controller based on VHDL
Platform: WINDOWS | Size: 176KB | Author: liu.hanzhong | Hits: 76

[VHDL-FPGA-Verilog] sdram_vhd_134

Description: Sound code of Xilinx Sdram Controller based on VHDL
Platform: WINDOWS | Size: 53KB | Author: liu.hanzhong | Hits: 114

[VHDL-FPGA-Verilog] DES

Description: DES encryption algorithm realization, uses hardware description language VHDL to compile
Platform: UNIX | Size: 23KB | Author: skyblue51 | Hits: 77

[VHDL-FPGA-Verilog] verhdl95

Description: vhdl
Platform: WINDOWS | Size: 25KB | Author: mcuxyb | Hits: 8

[VHDL-FPGA-Verilog] Interoperability of Verilog VHDL Procedural Langua

Description: vhdl
Platform: WINDOWS | Size: 13KB | Author: mcuxyb | Hits: 0

[VHDL-FPGA-Verilog] vhdl1

Description: Designs four ways according to the selector, its function is chooses four groups of different data according to the request an output Output that group of data has two controls signals to decide, its truth table as follows: Data access control end output data Input0 Input1 output 0 0 output0 0 1 output1 1 0 output 21 1 output 3
Platform: Others | Size: 27KB | Author: wuchenxi88 | Hits: 15

[VHDL-FPGA-Verilog] The original code

Description: 8051 core VHDL source code.
Platform: LINUX | Size: 95KB | Author: aixia1 | Hits: 78

[VHDL-FPGA-Verilog] fifo the original VHDL code

Description: In this paper, the source code for Verilog
Platform: LINUX | Size: 22KB | Author: aixia1 | Hits: 75

[VHDL-FPGA-Verilog] i2c Bus VHDL realization and VxWorks file system

Description: i2c bus VHDL realization and VxWorks file system
Platform: WINDOWS | Size: 16KB | Author: | Hits: 107