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wave_gen_ver_s6

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 173kb
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  • Author :vi***
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Introduction - If you have any usage issues, please Google them yourself
To generate waveform for the simulation of a signal
Packet file list
(Preview for download)
wave_gen_ver_s6\wave_gen_pins.ucf
...............\wave_gen_timing.ucf
...............\clk_div.v
...............\clk_gen.v
...............\clkx_bus.v
...............\cmd_parse.v
...............\dac_spi.v
...............\debouncer.v
...............\lb_ctl.v
...............\meta_harden.v
...............\out_ddr_flop.v
...............\reset_bridge.v
...............\resp_gen.v
...............\rst_gen.v
...............\samp_gen.v
...............\tb_cmd_gen.v
...............\tb_fifo.v
...............\tb_ram.v
...............\tb_resetgen.v
...............\tb_resp_checker.v
...............\tb_uart_driver.v
...............\tb_uart_monitor.v
...............\tb_wave_gen.v
...............\test_wave_gen.v
...............\to_bcd.v
...............\uart_baud_gen.v
...............\uart_rx.v
...............\uart_rx_ctl.v
...............\uart_tx.v
...............\uart_tx_ctl.v
...............\wave_gen.v
...............\wave_gen_ver_s6.xise
...............\readme
...............\clogb2.txt
...............\ipcore_dir
...............\..........\clk_core
...............\..........\........\doc
...............\..........\........\clk_core.ucf
...............\..........\........\clk_wiz_readme.txt
...............\..........\........\example_design
...............\..........\........\..............\clk_core_exdes.v
...............\..........\........\..............\clk_core_exdes.vhd
...............\..........\........\implement
...............\..........\........\.........\implement.bat
...............\..........\........\.........\implement.sh
...............\..........\........\.........\xst.prj
...............\..........\........\.........\xst.scr
...............\..........\........\simulation
...............\..........\........\..........\functional
...............\..........\........\..........\..........\simcmds.tcl
...............\..........\........\..........\..........\simulate_isim.sh
...............\..........\........\..........\..........\simulate_mti.do
...............\..........\........\..........\..........\simulate_ncsim.sh
...............\..........\........\..........\..........\simulate_vcs.sh
...............\..........\........\..........\..........\ucli_commands.key
...............\..........\........\..........\..........\vcs_session.tcl
...............\..........\........\..........\..........\wave.do
...............\..........\........\..........\..........\wave.sv
...............\..........\........\..........\clk_core_tb.v
...............\..........\........\..........\clk_core_tb.vhd
...............\..........\char_fifo.asy
...............\..........\char_fifo.gise
...............\..........\char_fifo.ncf
...............\..........\char_fifo.ngc
...............\..........\char_fifo.sym
...............\..........\char_fifo.v
...............\..........\char_fifo.veo
...............\..........\char_fifo.vhd
...............\..........\char_fifo.vho
...............\..........\char_fifo.xco
...............\..........\char_fifo.xise
...............\..........\char_fifo_flist.txt
...............\..........\char_fifo_readme.txt
...............\..........\char_fifo_xmdf.tcl
...............\..........\clk_core.asy
...............\..........\clk_core.ejp
...............\..........\clk_core.gise
...............\..........\clk_core.v
...............\..........\clk_core.veo
...............\..........\clk_core.vhd
...............\..........\clk_core.vho
...............\..........\clk_core.xco
...............\..........\clk_core.xise
...............\..........\clk_core_flist.txt
...............\..........\clk_core_xmdf.tcl
...............\..........\samp_ram.asy
...............\..........\samp_ram.gise
...............\..........\samp_ram.ncf
...............\..........\samp_ram.ngc
...............\..........\samp_ram.sym
...............\..........\samp_ram.v
...............\..........\samp_ram.veo
...............\..........\samp_ram.vhd
...............\..........\samp_ram.vho
...............\..........\samp_ram.xco
...............\..........\samp_ram.xise
...............\..........\samp_ram_flist.txt
...............\..........\samp_ra
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