12 Verilog HDL design example application source c

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Category : VHDL-FPGA-Verilog
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Update : 2012-11-26
Size : 122kb
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Verilog HDL design example application source code Jingjiang

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Filename	Size	Update
12\第10章\chipfifolmp\chipfifolmp.vwf
..\......\...........\lpm_fifo_dc0.v
..\......\...........\lpm_fifo_dc0_bb.v
..\......\........one\chipfifoone.v
..\......\...........\chipfifoone.vwf
..\......\....sramlmp\altdpram0.v
..\......\...........\altdpram0_bb.v
..\......\...........\chipsramlmp.vwf
..\......\........one\chipsramone.v
..\......\...........\chipsramone.vwf
..\......\outramone\outramone.v
..\......\.........\outramone.vwf
..\......\.........\testoutramone.v
..\......\shipromlmp\lpm_rom0.v
..\......\..........\lpm_rom0_bb.v
..\......\..........\shipromlmp.mif
..\......\..........\shipromlmp.vwf
..\......\.......one\chipromone.v
..\......\..........\chipromone.vwf
..\......\....sramone\db\shipsramone.db_info
..\......\...........\..\shipsramone.eco.cdb
..\......\...........\..\shipsramone.sld_design_entry.sci
..\......\异步FIFO设计\async_cmp.v
..\......\............\async_fifo.v
..\......\............\dp_ram.v
..\......\............\rptr_empty.v
..\......\............\wptr_full.v
..\...1章\CORDIC数字计算机的设计\cordic.v
..\......\I2C Master\i2c.v
..\......\..........\iicwr.vwf
..\......\..........\testi2c.v
..\......\manchester\manchester.qpf
..\......\..........\manchester.vwf
..\......\..........\mcode.v
..\......\..........\mdecode.v
..\......\RS(204	188)译码器的设计\BM_KES.v
..\......\.......................\CheinSearch.v
..\......\.......................\ff_mul.v
..\......\.......................\forney.v
..\......\.......................\ROM_INV.mif
..\......\.......................\rom_inv.v
..\......\.......................\rom_power.mif
..\......\.......................\rom_power.v
..\......\.......................\RS(204	188)译码器说明.txt
..\......\.......................\rs_decoder.v
..\......\.......................\SyndromeCalc.v
..\......\..编码器\mula_0.v
..\......\........\mula_1.v
..\......\........\mula_10.v
..\......\........\mula_11.v
..\......\........\mula_12.v
..\......\........\mula_13.v
..\......\........\mula_14.v
..\......\........\mula_15.v
..\......\........\mula_16.v
..\......\........\mula_17.v
..\......\........\mula_18.v
..\......\........\mula_2.v
..\......\........\mula_21.v
..\......\........\mula_22.v
..\......\........\mula_25.v
..\......\........\mula_3.v
..\......\........\mula_31.v
..\......\........\mula_32.v
..\......\........\mula_35.v
..\......\........\mula_38.v
..\......\........\mula_4.v
..\......\........\mula_45.v
..\......\........\mula_48.v
..\......\........\mula_5.v
..\......\........\mula_51.v
..\......\........\mula_59.v
..\......\........\mula_6.v
..\......\........\mula_61.v
..\......\........\mula_7.v
..\......\........\mula_8.v
..\......\........\mula_9.v
..\......\........\mul_encode.vhd
..\......\........\rscode.v
..\......\........\rscode.vhd
..\......\........\rscode.vwf
..\......\........\rstestbench.vhd
..\......\........\testbenchmul.vhd
..\......\........\testbenchmul_encode.vhd
..\......\SPI Master\clkdiv.v
..\......\..........\spi.vwf
..\......\..........\spimaster.v
..\......\UART\clkdiv.v
..\......\....\testuart.v
..\......\....\uartrx.v
..\......\....\uartrxtx.vwf
..\......\....\uarttx.v
..\......\伪随机序列应用设计\randomization.v
..\......\时序状态机\mealy_fsm1.v
..\......\..........\mealy_fsm2.v
..\......\积分梳状滤波器(CIC)设计\cic3_decimator.v
..\...2章\cefre\cefre.vwf
..\......\.....\cnt.v
..\......\.....\gate.v
..\......\..period\ceperiod.vwf

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