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VHDL-FPGA-Verilog
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Update : 2012-11-26
Size : 4.72mb
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Author :
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VHDL\VHDL.ppt
....\VHDL语言一览.doc
....\....链接\1段测试程序.ppt
....\........\3位计数器VHDL源代码.ppt
....\........\4选1多路选择器源码.doc
....\........\8位计数器原理图.ppt
....\........\FIFO模块框图.ppt
....\........\FIFO源码.doc
....\........\Mealy状态机的实例.ppt
....\........\Moore状态机的实例.ppt
....\........\三一八译码器VHDL源码.ppt
....\........\修改8位计数器实例.ppt
....\........\修改后的Mealy状态机源码.ppt
....\........\修改后的Moore状态机源码.ppt
....\........\修正后的VHDL代码.ppt
....\........\具有3个进程的Moore状态机.ppt
....\........\子类型测试程序.ppt
....\........\存储器地址译码器VHDL源码.ppt
....\........\执行测试矢量的测试平台.ppt
....\........\新建 Microsoft Office PowerPoint 演示文稿.pptx
....\........\用VHDL语言描述的双向缓冲器的源程序 .ppt
....\........\用when-else语句定义三态输出.ppt
....\........\用时钟同步输出信号的Mealy型状态机.ppt
....\........\用时钟同步输出信号的Moore型抶态机.`pt
....\........\直接把状态作为输出信号的状态机.ppt
....\........\采用双向的IO.ppt
....\~$ Microsoft Office Word 文档 (2).docx
....\作业习题模板.doc
....\新建 Microsoft Office Word 文档 (2).doc
....\新建 Microsoft Office Word 文档 (2).docx
....\新建 Microsoft Office Word 文档.docx
....\VHDL链接
VHDL
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