Environment based on QuartusII 6.0 vga drivers, the chips for the EP1C6Q240C8, development board clock 50M, the display mode 800* 600,72 Hz, the frequency content of screen displays several lines.

vga\vga.qpf
...\vga.qsf
...\db\vga.db_info
...\..\vga.cbx.xml
...\..\vga.hif
...\..\vga.hier_info
...\..\vga.psp
...\..\vga.dbp
...\..\vga.syn_hier_info
...\..\vga.cmp.kpt
...\..\vga.map.qmsg
...\..\vga.rtlv_sg.cdb
...\..\vga.rtlv.hdb
...\..\vga.rtlv_sg_swap.cdb
...\..\vga.pre_map.hdb
...\..\vga.pre_map.cdb
...\..\vga.map.logdb
...\..\vga.sgdiff.cdb
...\..\vga.sgdiff.hdb
...\..\vga.sld_design_entry_dsc.sci
...\..\vga.map.cdb
...\..\vga.map.hdb
...\..\vga.fit.qmsg
...\..\vga.cmp.logdb
...\..\vga.asm.qmsg
...\..\vga.tan.qmsg
...\..\vga.cmp.tdb
...\..\vga.cmp0.ddb
...\..\vga.cmp.cdb
...\..\vga.signalprobe.cdb
...\..\vga.cmp.hdb
...\..\vga.cmp.rdb
...\..\vga.sld_design_entry.sci
...\..\vga.eco.cdb
...\vga.vhd
...\vga.map.rpt
...\vga.flow.rpt
...\vga.map.summary
...\vga.pin
...\vga.fit.rpt
...\vga.fit.smsg
...\vga.fit.summary
...\vga.sof
...\vga.pof
...\vga.asm.rpt
...\vga.tan.summary
...\vga.tan.rpt
...\vga.done
...\vga.cdf
...\vga.qws
...\db
vga

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